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* [X86][SSE] Add support for combining scalar_to_vector(extract_vector_elt) ↵Simon Pilgrim2017-02-031-8/+3
| | | | | | | | into a target shuffle. Correctly flagging upper elements as undef. llvm-svn: 294020
* [X86][XOP] Added FIXME comments to missed shuffle combine opportunitiesSimon Pilgrim2017-02-021-0/+2
| | | | | | Requested by @silvas llvm-svn: 293916
* [X86][XOP] Add test showing failure to combine build vector to vpermil2ps ↵Simon Pilgrim2017-01-311-0/+28
| | | | | | shuffle llvm-svn: 293663
* [X86][XOP] Fix test nameSimon Pilgrim2017-01-301-3/+3
| | | | llvm-svn: 293533
* [X86][XOP] Add vpermil2ps target shuffle -> insertps combine testSimon Pilgrim2017-01-111-0/+14
| | | | llvm-svn: 291690
* [X86][SSE] Add support for combining target shuffles to SHUFPS.Simon Pilgrim2016-12-181-2/+6
| | | | | | As discussed on D27692, the next step will be to allow cross-domain shuffles once the combined shuffle depth passes a certain point. llvm-svn: 290064
* [X86][SSE] Fix domains for VZEXT_LOAD type instructionsSimon Pilgrim2016-12-151-1/+1
| | | | | | | | Add the missing domain equivalences for movss, movsd, movd and movq zero extending loading instructions. Differential Revision: https://reviews.llvm.org/D27684 llvm-svn: 289825
* [X86][SSE] Add support for combining target shuffles to SHUFPD.Simon Pilgrim2016-12-111-4/+4
| | | | llvm-svn: 289407
* [X86][XOP] Add target shuffle tests showing missing PSHUFPD combine.Simon Pilgrim2016-12-111-0/+28
| | | | llvm-svn: 289398
* [X86][XOP] Add permil2ps buildvector combine testSimon Pilgrim2016-12-101-0/+23
| | | | llvm-svn: 289327
* [X86][XOP] Fix VPERMIL2 non-constant pool shuffle decoding (PR31296)Simon Pilgrim2016-12-071-2/+8
| | | | | | | | The non-constant pool version of DecodeVPERMIL2PMask was not offsetting correctly for the second input. I've updated the code to match the implementation in the constant-pool version. Annoyingly this bug was hidden for so long as it's tricky to combine to useful variable shuffle masks that don't become constant-pool entries. llvm-svn: 288898
* [X86][XOP] Add test case for PR31296Simon Pilgrim2016-12-061-0/+20
| | | | llvm-svn: 288858
* [X86][SSE] Add support for combining target shuffles to UNPCKL/UNPCKH.Simon Pilgrim2016-12-051-4/+4
| | | | llvm-svn: 288663
* [X86][XOP] Add target shuffle tests showing missing UNPCKL combine.Simon Pilgrim2016-12-041-0/+14
| | | | llvm-svn: 288628
* [X86][SSE] Renamed shuffle combine test.Simon Pilgrim2016-12-021-6/+6
| | | | | | We're trying to combine to vpunpckhbw not vpunpckhwd llvm-svn: 288501
* [X86][SSE] Add support for target shuffle constant foldingSimon Pilgrim2016-11-301-28/+10
| | | | | | | | | | Initial support for target shuffle constant folding in cases where all shuffle inputs are constant. We may be able to relax this and merge shuffles with only some constant inputs in the future. I've added the helper function getTargetConstantBitsFromNode (based off a similar function in X86ShuffleDecodeConstantPool.cpp) that could be reused for other cases requiring constant vector extraction. Differential Revision: https://reviews.llvm.org/D27220 llvm-svn: 288250
* [X86][SSE] Always combine target shuffles to MOVSD/MOVSSSimon Pilgrim2016-10-011-4/+2
| | | | | | | | Now we can commute to BLENDPD/BLENDPS on SSE41+ targets if necessary, so simplify the combine matching where we can. This required me to add a couple of scalar math movsd/moss fold patterns that hadn't been needed in the past. llvm-svn: 283038
* [X86][SSE] Improve target shuffle mask extractionSimon Pilgrim2016-09-171-4/+1
| | | | | | Add ability to extract vXi64 'vzext_movl' masks on 32-bit targets llvm-svn: 281834
* [X86][XOP] Add target shuffle constant folding testsSimon Pilgrim2016-09-171-0/+90
| | | | llvm-svn: 281828
* [X86][XOP] Fix VPERMIL2PD mask creation on 32-bit targetsSimon Pilgrim2016-09-091-68/+155
| | | | | | Use getConstVector helper to correctly create v2i64/v4i64 constants on 32-bit targets llvm-svn: 281105
* [X86][XOP] Add support for combining target shuffles to VPERMIL2PD/VPERMIL2PSSimon Pilgrim2016-08-091-0/+30
| | | | llvm-svn: 278120
* [X86][XOP] Add support for combining target shuffles to VPPERMSimon Pilgrim2016-08-091-0/+12
| | | | llvm-svn: 278114
* [X86][SSE] Allow target shuffle combining to match masks with SM_Sentinel valuesSimon Pilgrim2016-06-191-1/+1
| | | | | | | | | | | | We currently only allow exact matches of shuffle mask patterns during target shuffle combining. This patch relaxes this to permit SM_SentinelUndef in the combined shuffle to always be accepted as well as allowing exact matching of the SM_SentinelZero value. I've adjusted some tests that were requiring exact shuffle masks to now include undef values. Differential Revision: http://reviews.llvm.org/D21495 llvm-svn: 273119
* [X86][SSE] Improved blend+zero target shuffle combining to use combined ↵Simon Pilgrim2016-06-071-1/+2
| | | | | | | | | | shuffle mask directly We currently only combine to blend+zero if the target value type has 8 elements or less, but this was missing a lot of cases where the combined mask had been widened. This change makes it so we use the combined mask to determine the blend value type, allowing us to catch more widened cases. llvm-svn: 272003
* [X86][XOP] Added VPERMIL2PD/VPERMIL2PS raw mask decoding for target shuffle ↵Simon Pilgrim2016-06-051-4/+1
| | | | | | combines llvm-svn: 271834
* [X86][XOP] Added VPERMIL2PD/VPERMIL2PS as a target shuffle typeSimon Pilgrim2016-06-051-10/+14
| | | | llvm-svn: 271831
* [X86][XOP] Added VPERMIL2PD/VPERMIL2PS shuffle mask comment decodingSimon Pilgrim2016-06-041-1/+1
| | | | llvm-svn: 271809
* [X86][XOP] Support for VPERMIL2PD/VPERMIL2PS 2-input shuffle instructionsSimon Pilgrim2016-06-031-22/+18
| | | | | | | | | | | | This patch begins adding support for lowering to the XOP VPERMIL2PD/VPERMIL2PS shuffle instructions - adding the X86ISD::VPERMIL2 opcode and cleaning up the usage. The internal llvm intrinsics were assuming the shuffle mask operand was the same type as the float/double input operands (I guess to simplify the intrinsic definitions in X86InstrXOP.td to a single value type). These needed changing to integer types (matching the clang builtin and the AMD intrinsics definitions), an auto upgrade path is added to convert old calls. Mask decoding/target shuffle support will be added in future patches. Differential Revision: http://reviews.llvm.org/D20049 llvm-svn: 271633
* [X86][XOP] Add placeholder VPERMIL2 combining testsSimon Pilgrim2016-05-031-0/+62
| | | | llvm-svn: 268450
* [X86][XOP] Fixed VPPERM permute op decoding (PR27472).Simon Pilgrim2016-04-241-1/+1
| | | | | | Fixed issue with VPPERM target shuffle mask decoding that was incorrectly masking off the 3-bit permute op with a 2-bit mask. llvm-svn: 267346
* [X86][SSE] Improved support for decoding target shuffle masks through bitcastsSimon Pilgrim2016-04-241-5/+1
| | | | | | | | Reused the ability to split constants of a type wider than the shuffle mask to work with masks generated from scalar constants transfered to xmm. This fixes an issue preventing PSHUFB target shuffle masks decoding rematerialized scalar constants and also exposes the XOP VPPERM bug described in PR27472. llvm-svn: 267343
* [X86][SSE] Demonstrate issue with decoding shuffle masks that have been ↵Simon Pilgrim2016-04-241-0/+15
| | | | | | | | lowered as rematerialized constants on scalar unit Found whilst investigating PR27472 llvm-svn: 267339
* [X86][XOP] Added VPPERM -> BLEND-WITH-ZERO TestSimon Pilgrim2016-04-231-0/+9
| | | | | | Currently failing due to poor blend matching, found whilst investigating PR27472 llvm-svn: 267282
* [X86][XOP] Added VPPERM constant mask decoding and target shuffle combining ↵Simon Pilgrim2016-04-161-3/+16
| | | | | | | | support Added additional test that peeks through bitcast to v16i8 mask llvm-svn: 266533
* [X86][XOP] Support for VPPERM 2-input shuffle mask decodingSimon Pilgrim2016-04-091-4/+4
| | | | | | | | | | This patch adds support for decoding XOP VPPERM instruction when it represents a basic shuffle. The mask decoding required the existing MCInstrLowering code to be updated to support binary shuffles - the implementation now matches what is done in X86InstrComments.cpp. Differential Revision: http://reviews.llvm.org/D18441 llvm-svn: 265874
* [X86][XOP] Support for VPPERM byte shuffle instructionSimon Pilgrim2016-03-241-2/+11
| | | | | | | | This patch begins adding support for lowering to the XOP VPPERM instruction - adding the X86ISD::VPPERM opcode. Differential Revision: http://reviews.llvm.org/D18189 llvm-svn: 264260
* [X86][XOP] Added target shuffle combine tests for XOP's VPPERM 2-op shuffleSimon Pilgrim2016-03-141-0/+31
Actual combing support will be added in a future patch llvm-svn: 263402
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