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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-12-06 22:50:13 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-12-06 22:50:13 +0000 |
| commit | 0559b9e557addc6093db2667b0a22a8a4e6ca9d4 (patch) | |
| tree | c8b39521b68e644d8f2299c23a4ef5bfd801ef56 /llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll | |
| parent | 0a76e3241f05a996a2a507a5c32476326d2b3355 (diff) | |
| download | bcm5719-llvm-0559b9e557addc6093db2667b0a22a8a4e6ca9d4.tar.gz bcm5719-llvm-0559b9e557addc6093db2667b0a22a8a4e6ca9d4.zip | |
[X86][XOP] Add test case for PR31296
llvm-svn: 288858
Diffstat (limited to 'llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll index 707cafe9931..41c1866de0d 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll @@ -341,3 +341,23 @@ define <16 x i8> @constant_fold_vpperm() { %1 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> <i8 0, i8 -1, i8 -2, i8 -3, i8 -4, i8 -5, i8 -6, i8 -7, i8 -8, i8 -9, i8 -10, i8 -11, i8 -12, i8 -13, i8 -14, i8 -15>, <16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, <16 x i8> <i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16>) ret <16 x i8> %1 } + +define <4 x float> @PR31296(i8* %in) { +; X32-LABEL: PR31296: +; X32: # BB#0: # %entry +; X32-NEXT: vmovaps {{.*#+}} xmm0 = [1.000000e+00,0.000000e+00,0.000000e+00,1.000000e+00] +; X32-NEXT: retl +; +; X64-LABEL: PR31296: +; X64: # BB#0: # %entry +; X64-NEXT: vmovaps {{.*#+}} xmm0 = [1.000000e+00,0.000000e+00,0.000000e+00,1.000000e+00] +; X64-NEXT: retq +entry: + %0 = getelementptr i8, i8* %in, i32 0 + %1 = bitcast i8* %0 to i32* + %2 = load i32, i32* %1 + %3 = zext i32 %2 to i128 + %4 = bitcast i128 %3 to <4 x float> + %5 = shufflevector <4 x float> %4, <4 x float> <float 0.000000e+00, float 1.000000e+00, float undef, float undef>, <4 x i32> <i32 0, i32 4, i32 4, i32 5> + ret <4 x float> %5 +} |
