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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-10-01 15:33:01 +0000 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-10-01 15:33:01 +0000 |
commit | ae17cf20ce6bd2fb9b7660fa124859916ae1c74a (patch) | |
tree | 54330987fb8ec1d8be491551502b7b17f1bafbc2 /llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll | |
parent | ccdd1ff49b2cebd46eb3b3972680cc07abff8a5e (diff) | |
download | bcm5719-llvm-ae17cf20ce6bd2fb9b7660fa124859916ae1c74a.tar.gz bcm5719-llvm-ae17cf20ce6bd2fb9b7660fa124859916ae1c74a.zip |
[X86][SSE] Always combine target shuffles to MOVSD/MOVSS
Now we can commute to BLENDPD/BLENDPS on SSE41+ targets if necessary, so simplify the combine matching where we can.
This required me to add a couple of scalar math movsd/moss fold patterns that hadn't been needed in the past.
llvm-svn: 283038
Diffstat (limited to 'llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll')
-rw-r--r-- | llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll b/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll index 121fafc84c5..c1d4446023d 100644 --- a/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll @@ -262,15 +262,13 @@ define <2 x double> @constant_fold_vpermil2pd() { ; X32-LABEL: constant_fold_vpermil2pd: ; X32: # BB#0: ; X32-NEXT: vmovapd {{.*#+}} xmm0 = [-2.000000e+00,-1.000000e+00] -; X32-NEXT: vmovapd {{.*#+}} xmm1 = [1.000000e+00,2.000000e+00] -; X32-NEXT: vpermil2pd {{.*#+}} xmm0 = xmm0[0],xmm1[1] +; X32-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],mem[1] ; X32-NEXT: retl ; ; X64-LABEL: constant_fold_vpermil2pd: ; X64: # BB#0: ; X64-NEXT: vmovapd {{.*#+}} xmm0 = [-2.000000e+00,-1.000000e+00] -; X64-NEXT: vmovapd {{.*#+}} xmm1 = [1.000000e+00,2.000000e+00] -; X64-NEXT: vpermil2pd {{.*#+}} xmm0 = xmm0[0],xmm1[1] +; X64-NEXT: vblendpd {{.*#+}} xmm0 = xmm0[0],mem[1] ; X64-NEXT: retq %1 = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> <double 1.0, double 2.0>, <2 x double> <double -2.0, double -1.0>, <2 x i64> <i64 4, i64 2>, i8 2) ret <2 x double> %1 |