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* [x86] regenerate checks with update_llc_test_checks.pySanjay Patel2017-06-121-22/+1
| | | | | | | | | | The dream of a unified check-line auto-generator for all phases of compilation is dead. The llc script has already diverged to be better at its goal, so having 2 scripts that do almost the same thing is just causing confusion for newcomers. I plan to fix up more x86 tests in a next commit. We can rip out the llc ability in update_test_checks.py after that. llvm-svn: 305202
* [X86][SSE] Fix domains for VZEXT_LOAD type instructionsSimon Pilgrim2016-12-151-1/+1
| | | | | | | | Add the missing domain equivalences for movss, movsd, movd and movq zero extending loading instructions. Differential Revision: https://reviews.llvm.org/D27684 llvm-svn: 289825
* [X86][SSE] Consistently set MOVD/MOVQ load/store/move instructions to ↵Simon Pilgrim2016-12-071-3/+3
| | | | | | | | | | integer domain We are being inconsistent with these instructions (and all their variants.....) with a random mix of them using the default float domain. Differential Revision: https://reviews.llvm.org/D27419 llvm-svn: 288902
* [x86] allow FP-logic ops when one operand is FP and result is FPSanjay Patel2016-11-161-12/+6
| | | | | | | | | | | | | | We save an inter-register file move this way. If there's any CPU where the FP logic is slower, we could transform this back to int-logic in MachineCombiner. This helps, but doesn't solve, PR6137: https://llvm.org/bugs/show_bug.cgi?id=6137 The 'andn' test shows that we're missing a pattern match to recognize the xor with -1 constant as a 'not' op. llvm-svn: 287171
* [x86] add fake scalar FP logic instructions to ReplaceableInstrs to save ↵Sanjay Patel2016-11-161-1/+1
| | | | | | | | | | | | | | | | | | | some bytes We can replace "scalar" FP-bitwise-logic with other forms of bitwise-logic instructions. Scalar SSE/AVX FP-logic instructions only exist in your imagination and/or the bowels of compilers, but logically equivalent int, float, and double variants of bitwise-logic instructions are reality in x86, and the float variant may be a shorter instruction depending on which flavor (SSE or AVX) of vector ISA you have...so just prefer float all the time. This is a preliminary step towards solving PR6137: https://llvm.org/bugs/show_bug.cgi?id=6137 Differential Revision: https://reviews.llvm.org/D26712 llvm-svn: 287122
* [x86] regenerate checks; NFCSanjay Patel2016-11-151-18/+19
| | | | llvm-svn: 287051
* [X86] Remove the Fv packed logical operation alias instructions. Replace ↵Craig Topper2016-08-091-1/+1
| | | | | | | | them with patterns to the regular instructions. This enables execution domain fixing which is why the tests changed. llvm-svn: 278090
* [x86] enable bitcasted fabs/fneg transformsSanjay Patel2016-06-101-4/+2
| | | | | | | The vector cases don't change because we already have folds in X86ISelLowering to look through and remove bitcasts. llvm-svn: 272427
* [x86] add tests to show current codegen for obscured fneg/fabsSanjay Patel2016-05-041-0/+50
| | | | llvm-svn: 268533
* [x86] replace integer logic ops with packed SSE FP logic opsSanjay Patel2015-10-271-18/+12
| | | | | | | | | | | | | | | | | | | If we have an operand to a bitwise logic op that's already in an XMM register and the result is going to be sent to an XMM register, then use an SSE logic op to avoid moves between the integer and vector register files. Related commits: http://reviews.llvm.org/rL248395 http://reviews.llvm.org/rL248399 http://reviews.llvm.org/rL248404 http://reviews.llvm.org/rL248409 http://reviews.llvm.org/rL248415 This should solve PR22428: https://llvm.org/bugs/show_bug.cgi?id=22428 llvm-svn: 251378
* add FP logic test cases to show current codegen (PR22428)Sanjay Patel2015-10-261-0/+60
| | | | llvm-svn: 251370
* [x86] replace integer 'xor' ops with packed SSE FP 'xor' ops when operating ↵Sanjay Patel2015-09-231-4/+1
| | | | | | | | | | | | | | | | | | | | | | | on FP scalars Turn this: movd %xmm0, %eax movd %xmm1, %ecx xorl %eax, %ecx movd %ecx, %xmm0 into this: xorps %xmm1, %xmm0 This is related to, but does not solve: https://llvm.org/bugs/show_bug.cgi?id=22428 This is an extension of: http://reviews.llvm.org/rL248395 llvm-svn: 248415
* [x86] replace integer 'or' ops with packed SSE FP 'or' ops when operating on ↵Sanjay Patel2015-09-231-4/+1
| | | | | | | | | | | | | | | | | | | | | | | FP scalars Turn this: movd %xmm0, %eax movd %xmm1, %ecx orl %eax, %ecx movd %ecx, %xmm0 into this: orps %xmm1, %xmm0 This is related to, but does not solve: https://llvm.org/bugs/show_bug.cgi?id=22428 This is an extension of: http://reviews.llvm.org/rL248395 llvm-svn: 248409
* [x86] replace integer 'and' ops with packed SSE FP 'and' ops when operating ↵Sanjay Patel2015-09-231-11/+4
| | | | | | | | | | | | | | | | | | | | | on FP scalars Turn this: movd %xmm0, %eax movd %xmm1, %ecx andl %eax, %ecx movd %ecx, %xmm0 into this: andps %xmm1, %xmm0 This is related to, but does not solve: https://llvm.org/bugs/show_bug.cgi?id=22428 Differential Revision: http://reviews.llvm.org/D13065 llvm-svn: 248395
* add test file ahead of any functional changes for PR22428Sanjay Patel2015-09-201-0/+223
llvm-svn: 248123
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