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| author | Sanjay Patel <spatel@rotateright.com> | 2016-11-16 22:34:05 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-11-16 22:34:05 +0000 |
| commit | 066139a3ec1ea686e670bfb8afd5637463b65425 (patch) | |
| tree | 8c7bccdfabbffb1d6f3b63eba0ae548503cd3116 /llvm/test/CodeGen/X86/fp-logic.ll | |
| parent | f33f91af245d631034bd55eedc4f9705461d17f6 (diff) | |
| download | bcm5719-llvm-066139a3ec1ea686e670bfb8afd5637463b65425.tar.gz bcm5719-llvm-066139a3ec1ea686e670bfb8afd5637463b65425.zip | |
[x86] allow FP-logic ops when one operand is FP and result is FP
We save an inter-register file move this way. If there's any CPU where
the FP logic is slower, we could transform this back to int-logic in
MachineCombiner.
This helps, but doesn't solve, PR6137:
https://llvm.org/bugs/show_bug.cgi?id=6137
The 'andn' test shows that we're missing a pattern match to
recognize the xor with -1 constant as a 'not' op.
llvm-svn: 287171
Diffstat (limited to 'llvm/test/CodeGen/X86/fp-logic.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/fp-logic.ll | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/llvm/test/CodeGen/X86/fp-logic.ll b/llvm/test/CodeGen/X86/fp-logic.ll index 2c6698fb120..301fa8f4137 100644 --- a/llvm/test/CodeGen/X86/fp-logic.ll +++ b/llvm/test/CodeGen/X86/fp-logic.ll @@ -3,13 +3,9 @@ ; PR22428: https://llvm.org/bugs/show_bug.cgi?id=22428 ; f1, f2, f3, and f4 should use an integer logic instruction. -; f9 and f10 should use an FP (SSE) logic instruction. +; f5, f6, f9, and f10 should use an FP (SSE) logic instruction. ; -; f5, f6, f7, and f8 are less clear. -; -; For f5 and f6, we can save a register move by using an FP logic instruction, -; but we may need to calculate the relative costs of an SSE op vs. int op vs. -; scalar <-> SSE register moves. +; f7 and f8 are less clear. ; ; For f7 and f8, the SSE instructions don't take immediate operands, so if we ; use one of those, we either have to load a constant from memory or move the @@ -79,9 +75,8 @@ define i32 @f4(float %x) { define float @f5(float %x, i32 %y) { ; CHECK-LABEL: f5: ; CHECK: # BB#0: -; CHECK-NEXT: movd %xmm0, %eax -; CHECK-NEXT: andl %edi, %eax -; CHECK-NEXT: movd %eax, %xmm0 +; CHECK-NEXT: movd %edi, %xmm1 +; CHECK-NEXT: andps %xmm1, %xmm0 ; CHECK-NEXT: retq ; %bc1 = bitcast float %x to i32 @@ -95,9 +90,8 @@ define float @f5(float %x, i32 %y) { define float @f6(float %x, i32 %y) { ; CHECK-LABEL: f6: ; CHECK: # BB#0: -; CHECK-NEXT: movd %xmm0, %eax -; CHECK-NEXT: andl %edi, %eax -; CHECK-NEXT: movd %eax, %xmm0 +; CHECK-NEXT: movd %edi, %xmm1 +; CHECK-NEXT: andps %xmm1, %xmm0 ; CHECK-NEXT: retq ; %bc1 = bitcast float %x to i32 |
