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path: root/llvm/test/CodeGen/X86/combine-sdiv.ll
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* [X86][AVX] insert_subvector(bitcast(v), bitcast(s), c1) -> bitcast(insert_sub...Simon Pilgrim2019-01-311-12/+6
* [X86][SSE] Improve immediate vector shift known bits handling.Simon Pilgrim2018-12-171-34/+25
* [TargetLowering] Add DemandedElts mask to SimplifyDemandedBits (PR40000)Simon Pilgrim2018-12-171-6/+0
* [TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-151-172/+151
* [SelectionDAG] Improve SimplifyDemandedBits to SimplifyDemandedVectorElts sim...Simon Pilgrim2018-12-011-116/+114
* [X86] Emit PACKUS directly from the v16i8 LowerMULH code instead of using a s...Craig Topper2018-11-301-2/+1
* [SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from Leg...Craig Topper2018-11-291-1/+2
* [DAG] consolidate shift simplificationsSanjay Patel2018-11-231-346/+297
* [X86] Preserve undef information when creating a punpckl/hbw from a v16i8 whe...Craig Topper2018-11-201-5/+1
* [X86] Replace more calls to getZeroVector with regular getConstant.Craig Topper2018-11-201-26/+21
* [X86] In LowerMULH, use generic truncate and vector shuffle nodes instead of ...Craig Topper2018-11-121-2/+2
* [DAGCombiner] Fold 0 div/rem X to 0David Bolvansky2018-10-311-80/+6
* [DAGCombiner] Improve X div/rem Y fold if single bit element typeDavid Bolvansky2018-10-301-309/+3
* [X86] Move promotion of vector and/or/xor from legalization to DAG combineCraig Topper2018-10-151-4/+9
* [DAGCombiner][NFC] Tests for X div/rem Y single bit foldDavid Bolvansky2018-09-291-0/+324
* [X86][SSE] Use ISD::MULHS for constant vXi16 ISD::SRA lowering (PR38151)Simon Pilgrim2018-09-261-234/+137
* [X86] Handle COPYs of physregs better (regalloc hints)Simon Pilgrim2018-09-191-1/+1
* [X86] Add initial SimplifyDemandedVectorEltsForTargetNode supportSimon Pilgrim2018-09-191-154/+125
* [DAGCombiner] Add X / X -> 1 & X % X -> 0 foldsSimon Pilgrim2018-08-291-83/+19
* [X86][SSE] LowerMULH vXi8 - use SSE shifts directly.Simon Pilgrim2018-08-221-46/+9
* [X86][SSE] Add sdiv test case from PR38658Simon Pilgrim2018-08-221-0/+202
* [X86] Add SSE2 sdiv combine testsSimon Pilgrim2018-08-211-651/+1452
* [TargetLowering] Add BuildSDiv support for division by one or negone.Simon Pilgrim2018-08-211-115/+92
* [TargetLowering] Disable BuildSDiv division by one or negone.Simon Pilgrim2018-08-201-80/+116
* [X86][SSE] Lower constant vXi8 ISD::SRL/ISD::SRA using PMULLWSimon Pilgrim2018-08-171-177/+76
* [TargetLowering] Add support for non-uniform vectors to BuildSDIVSimon Pilgrim2018-08-161-854/+372
* [X86][SSE] Add sdiv by nonuniform constant vector test containing -1/+1 and a...Simon Pilgrim2018-08-161-0/+125
* [X86][SSE] Add sdiv by nonuniform constant vector testsSimon Pilgrim2018-08-151-0/+789
* [X86] Add tests showing missing div/rem 0, X -> 0 combinesSimon Pilgrim2018-08-131-0/+67
* [X86][SSE] Use ISD::MULHU for constant/non-zero ISD::SRL lowering (PR38151)Simon Pilgrim2018-07-311-395/+209
* [X86][XOP] Fix SUB constant folding for VPSHA/VPSHL shift loweringSimon Pilgrim2018-07-201-110/+90
* [DAGCombiner] visitSDIV - Permit MIN_SIGNED_VALUE in pow2 vector codegenSimon Pilgrim2018-07-031-177/+206
* [DAGCombiner] Handle correctly non-splat power of 2 -1 divisor (PR37119)Simon Pilgrim2018-06-301-268/+80
* [DAGCombiner] Ensure we use the correct CC result type in visitSDIV (REAPPLIED)Simon Pilgrim2018-06-281-6/+19
* Revert "[DAGCombiner] Ensure we use the correct CC result type in visitSDIV"Haojian Wu2018-06-281-19/+6
* [DAGCombiner] Ensure we use the correct CC result type in visitSDIVSimon Pilgrim2018-06-281-6/+19
* [DAGCombiner] visitSDIV - add special case handling for (sdiv X, 1) -> X in p...Simon Pilgrim2018-06-271-3535/+1415
* [X86][SSE] Include MIN_SIGNED element in non-uniform SDIV pow2 testsSimon Pilgrim2018-06-271-25/+17
* [DAGCombiner] Fold SDIV(%X, MIN_SIGNED) -> SELECT(%X == MIN_SIGNED, 1, 0)Simon Pilgrim2018-06-271-54/+12
* [DAGCombiner] Don't accept signbit sdiv divisors in sdiv-by-pow2 vector expan...Simon Pilgrim2018-06-271-17/+63
* [X86] Add test for SDIV by sign bit (minsigned) valueSimon Pilgrim2018-06-261-0/+37
* [DAGCombiner] Don't accept -1 sdiv divisors in sdiv-by-pow2 vector expansion ...Simon Pilgrim2018-06-261-192/+185
* [X86][SSE] Add another sdiv by (nonuniform) minus one test (PR37119)Simon Pilgrim2018-06-261-2/+204
* [X86][SSE] Add sdiv by (nonuniform) minus one tests (PR37119)Simon Pilgrim2018-06-221-0/+297
* [X86][SSE] Regenerate sdiv combine testsSimon Pilgrim2018-05-291-65/+65
* [DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisorHeejin Ahn2018-04-271-1369/+3623
* DAGCombiner: Combine SDIV with non-splat vector pow2 divisorZvi Rackover2018-04-081-3570/+1316
* X86 Tests: Add a case for combining sdiv by a splatted pow2 negative. NFC.Zvi Rackover2018-04-051-0/+25
* [x86] consolidate and add tests for undef binop folds; NFCSanjay Patel2018-02-081-35/+0
* X86 Tests: Add AVX+XOP config to SDIV combine testsZvi Rackover2018-01-251-0/+622
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