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path: root/llvm/test/CodeGen/X86/combine-bitselect.ll
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* [X86] Add broadcast load folding patterns to the NoVLX compare patterns.Craig Topper2019-10-021-4/+2
| | | | | | | | | These patterns use zmm registers for 128/256-bit compares when the VLX instructions aren't available. Previously we only supported registers, but as PR36191 notes we can fold broadcast loads, but not regular loads. llvm-svn: 373423
* [X86] Move bitselect matching to vpternlog into X86ISelDAGToDAG.cppCraig Topper2019-09-291-3/+3
| | | | | | | | | | | | This allows us to reduce the use count on the condition node before the match. This enables load folding for that operand without relying on the peephole pass. This will be improved on for broadcast load folding in a subsequent commit. This still requires a bunch of isel patterns for vXi16/vXi8 types though. llvm-svn: 373156
* [X86] Enable canonicalizeBitSelect for AVX512 since we can use VPTERNLOG now.Craig Topper2019-09-291-14/+6
| | | | llvm-svn: 373155
* [X86][AVX] getTargetConstantBitsFromNode - extract bits from ↵Simon Pilgrim2019-04-101-71/+47
| | | | | | X86ISD::SUBV_BROADCAST llvm-svn: 358096
* [X86] Update the test case for v4i1 bitselect in combine-bitselect.ll to not ↵Craig Topper2019-04-031-62/+48
| | | | | | | | | | have an infinite loop in IR. In fact we don't even need a loop at all. I backed out the bug fix this was testing for and verified that this new case hit the same issue. This should stop D59626 from deleting some of this code by realizing it was dead due to the loop. llvm-svn: 357544
* [X86] canonicalizeBitSelect - don't attempt to canonicalize mask registersSimon Pilgrim2019-03-211-0/+82
| | | | | | | | We don't use X86ISD::ANDNP for mask registers. Test case from @craig.topper (Craig Topper) llvm-svn: 356696
* [X86][SSE] Canonicalize OR(AND(X,C),AND(Y,~C)) -> OR(AND(X,C),ANDNP(C,Y))Simon Pilgrim2019-01-221-137/+138
| | | | | | | | | | For constant bit select patterns, replace one AND with a ANDNP, allowing us to reuse the constant mask. Only do this if the mask has multiple uses (to avoid losing load folding) or if we have XOP as its VPCMOV can handle most folding commutations. This also requires computeKnownBitsForTargetNode support for X86ISD::ANDNP and X86ISD::FOR to prevent regressions in fabs/fcopysign patterns. Differential Revision: https://reviews.llvm.org/D55935 llvm-svn: 351819
* [X86] Add OR(AND(X,C),AND(Y,~C)) bit select testsSimon Pilgrim2019-01-071-0/+592
Based off work for D55935 llvm-svn: 350548
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