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| author | Craig Topper <craig.topper@intel.com> | 2019-10-02 04:45:02 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-10-02 04:45:02 +0000 |
| commit | 8d6a863b02f199960590973f06b4c4dd29df578f (patch) | |
| tree | 283d96188ef8f25d2438d73b1e0d42b9d47d6c46 /llvm/test/CodeGen/X86/combine-bitselect.ll | |
| parent | c3aab6eaaa0fedf009ced78e56dacc378a8cde8a (diff) | |
| download | bcm5719-llvm-8d6a863b02f199960590973f06b4c4dd29df578f.tar.gz bcm5719-llvm-8d6a863b02f199960590973f06b4c4dd29df578f.zip | |
[X86] Add broadcast load folding patterns to the NoVLX compare patterns.
These patterns use zmm registers for 128/256-bit compares when
the VLX instructions aren't available. Previously we only
supported registers, but as PR36191 notes we can fold broadcast
loads, but not regular loads.
llvm-svn: 373423
Diffstat (limited to 'llvm/test/CodeGen/X86/combine-bitselect.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/combine-bitselect.ll | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/X86/combine-bitselect.ll b/llvm/test/CodeGen/X86/combine-bitselect.ll index ccb969b747f..b65a7504b24 100644 --- a/llvm/test/CodeGen/X86/combine-bitselect.ll +++ b/llvm/test/CodeGen/X86/combine-bitselect.ll @@ -608,10 +608,8 @@ define <4 x i1> @bitselect_v4i1_loop(<4 x i32> %a0, <4 x i32> %a1) { ; AVX512F: # %bb.0: # %bb ; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 -; AVX512F-NEXT: vpbroadcastd {{.*#+}} xmm2 = [12,12,12,12] -; AVX512F-NEXT: vpcmpeqd %zmm2, %zmm1, %k1 -; AVX512F-NEXT: vpbroadcastd {{.*#+}} xmm2 = [15,15,15,15] -; AVX512F-NEXT: vpcmpeqd %zmm2, %zmm1, %k2 +; AVX512F-NEXT: vpcmpeqd {{.*}}(%rip){1to16}, %zmm1, %k1 +; AVX512F-NEXT: vpcmpeqd {{.*}}(%rip){1to16}, %zmm1, %k2 ; AVX512F-NEXT: vptestnmd %zmm0, %zmm0, %k0 {%k2} ; AVX512F-NEXT: vptestmd %zmm0, %zmm0, %k1 {%k1} ; AVX512F-NEXT: korw %k0, %k1, %k1 |
