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path: root/llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll
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* [X86][AVX] Push sign extensions of comparison bool results through bitops (PR...Simon Pilgrim2019-10-051-93/+68
* [X86][AVX] combineBitcastvxi1 - peek through bitops to determine size of orig...Simon Pilgrim2019-05-261-16/+12
* [x86] add more movmsk tests; NFCSanjay Patel2019-01-181-11/+313
* [X86] Allow combinevxi1Bitcast to use pmovmskb on avx512 targets if the input...Craig Topper2019-01-051-9/+1
* [DAGCombiner] allow hoisting vector bitwise logic ahead of truncatesSanjay Patel2018-12-161-62/+47
* [TargetLowering] Add ISD::OR + ISD::XOR handling to SimplifyDemandedVectorEltsSimon Pilgrim2018-12-151-12/+8
* [X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in...Craig Topper2018-10-091-1/+1
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-23/+23
* [X86] Legalize v32i1 without BWI via splitting to v16i1 rather than the defau...Craig Topper2018-01-231-18/+12
* [X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all si...Craig Topper2018-01-011-2/+0
* [X86] Add a DAG combine to widen (i4 (bitcast (v4i1))) before type legalizati...Craig Topper2017-12-311-8/+4
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-19/+19
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-28/+28
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-19/+19
* Revert "Correct dwarf unwind information in function epilogue for X86"Reid Kleckner2017-11-081-1/+0
* Reland "Correct dwarf unwind information in function epilogue for X86"Petar Jovanovic2017-11-071-0/+1
* Revert "Correct dwarf unwind information in function epilogue for X86"Petar Jovanovic2017-11-011-1/+0
* Correct dwarf unwind information in function epilogue for X86Petar Jovanovic2017-11-011-0/+1
* [X86][AVX512] Regenerate tests to remove retl/retq regexSimon Pilgrim2017-10-311-28/+28
* [X86][AVX512] Split AVX512F and AVX512BW bool-vector bitcast testsSimon Pilgrim2017-10-311-50/+131
* [SelectionDAG] Support 'bit preserving' floating points bitcasts on computeKn...Simon Pilgrim2017-10-281-44/+13
* [X86] truncateVectorCompareWithPACKSS - use PACKSSDW/PACKSSWB instead of just...Simon Pilgrim2017-10-241-12/+12
* [X86][SSE] combineBitcastvxi1 - use PACKSSWB directly to pack v8i16 to v16i8Simon Pilgrim2017-10-231-34/+18
* [X86][SSE] Regenerate bitcast-and-setcc testsSimon Pilgrim2017-10-231-24/+24
* [X86][SSE] Add support for lowering v8i16 binary shuffles to PACKSS/PACKUSSimon Pilgrim2017-10-041-12/+4
* [X86][SSE] Add support for lowering shuffles to PACKSS/PACKUSSimon Pilgrim2017-10-031-57/+25
* [SelectionDAG] Add BITCAST handling to ComputeNumSignBits for splatted sign b...Simon Pilgrim2017-09-181-48/+6
* [X86][SSE] Add pre-AVX2 support for (i32 bitcast(v32i1)) -> 2xMOVMSKSimon Pilgrim2017-07-211-216/+11
* [X86][SSE] Dropped -mcpu from bitcast+setcc mask testsSimon Pilgrim2017-07-051-52/+52
* Reverting commit 306414 on behalf of @gadi.haberMichael Zuckerman2017-06-281-1/+1
* Updated and extended the information about each instruction in HSW and SNB to...Gadi Haber2017-06-271-1/+1
* [X86] Match bitcast of vxi1 to pmovmskZvi Rackover2017-06-011-258/+565
* [X86] Add tests for (ix bitcast (vxi1 and ...)). NFC.Zvi Rackover2017-05-291-0/+403
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