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path: root/llvm/test/CodeGen/X86/avx512-trunc.ll
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* [x86] split 256-bit store of concatenated vectorsSanjay Patel2019-06-041-9/+7
* Revert "[x86] split 256-bit store of concatenated vectors"Sanjay Patel2019-05-281-7/+9
* [x86] split 256-bit store of concatenated vectorsSanjay Patel2019-05-281-9/+7
* [LegalizeVectorTypes] Have SplitVecOp_TruncateHelper fall back to SplitVecOp_...Craig Topper2018-11-221-93/+37
* [X86] Move the promotion of v16i16->v16i8 for avx512f but not avx512bw from l...Craig Topper2018-11-091-7/+7
* [X86] Turn X86ISD::VSEXT into X86ISD::VZEXT if the upper bits aren't demanded.Craig Topper2018-11-091-6/+6
* [X86] Improve unsigned saturation downconvert detection.Artur Gainullin2018-05-151-30/+15
* [X86] Tests for unsigned saturation downconvert detection.Artur Gainullin2018-04-141-4/+32
* [X86] Tests for unsigned saturation downconvert detection.Artur Gainullin2018-04-141-0/+310
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-15/+15
* [X86] Use ISD::TRUNCATE instead of X86ISD::VTRUNC when input and output types...Craig Topper2018-01-141-4/+2
* [X86] Add X86ISD::VTRUNC to computeKnownBitsForTargetNode.Craig Topper2018-01-141-2/+2
* X86 Tests: Update more isel tests with FastVariableShuffle featureZvi Rackover2018-01-091-1/+1
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-15/+15
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-77/+77
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-15/+15
* [X86][SSE] Add support for lowering shuffles to PACKSS/PACKUSSimon Pilgrim2017-10-031-1/+1
* Regenerate test (missing broadcast constant comments). NFCI.Simon Pilgrim2017-10-021-3/+3
* [X86] Teach execution domain fixing to convert between VPERMILPS and VPSHUFD.Craig Topper2017-09-181-2/+2
* [AVX512] Don't switch unmasked subvector insert/extract instructions when AVX...Craig Topper2017-08-171-21/+10
* [X86] Generate VZEROUPPER for Skylake-avx512.Amjad Aboud2017-03-031-0/+48
* [X86 Codegen] Fixed a bug in unsigned saturationElena Demikhovsky2017-01-291-4/+6
* Recommiting unsigned saturation with a bugfix.Elena Demikhovsky2017-01-191-0/+227
* Revert r291670 because it introduces a crash.Michael Kuperstein2017-01-181-205/+0
* X86 CodeGen: Optimized pattern for truncate with unsigned saturation.Elena Demikhovsky2017-01-111-0/+205
* Revert r291092 because it introduces a crash.Michael Kuperstein2017-01-091-107/+0
* AVX-512: Optimized pattern for truncate with unsigned saturation.Elena Demikhovsky2017-01-051-0/+107
* [AVX512] Add ExeDomain to vector extend and truncate instructions.Craig Topper2016-07-221-6/+6
* [X86][SSE] Allow folding of store/zext with PEXTRW of 0'th elementSimon Pilgrim2016-07-211-2/+1
* VirtRegMap: Replace some identity copies with KILL instructions.Matthias Braun2016-07-091-0/+15
* Make utils/update_llc_test_checks.py note that the assertions areJames Y Knight2015-11-231-0/+1
* AVX-512: Optimized SIMD truncate operations for AVX512F set.Elena Demikhovsky2015-11-011-76/+199
* AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Trunc...Igor Breger2015-07-241-0/+364
* Revert r242990: "AVX-512: Implemented encoding , DAG lowering and ..."Chandler Carruth2015-07-231-364/+0
* AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Trunc...Igor Breger2015-07-231-0/+364
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