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path: root/llvm/test/CodeGen/X86/avx-schedule.ll
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* [X86][BtVer2] X86ISD::VPERMILPV has local forwarding disabledSimon Pilgrim2019-01-221-8/+8
* [X86][BtVer2] Update latency of horizontal operations.Andrea Di Biagio2019-01-161-8/+8
* [X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX.Clement Courbet2018-11-091-42/+42
* AMD BdVer2 (Piledriver) Initial Scheduler modelRoman Lebedev2018-10-271-313/+313
* [NFC][X86] Baseline tests for AMD BdVer2 (Piledriver) Scheduler modelRoman Lebedev2018-10-271-0/+607
* [x86] make blend tests resistant to demanded elements improvements; NFCSanjay Patel2018-10-051-18/+18
* [X86][Sched] Update scheduling information for VZEROALL on HWS, BDW, SKX, SNB.Clement Courbet2018-10-011-5/+5
* [X86][Sched] Add zero idiom sched data to the SNB model.Clement Courbet2018-09-211-8/+8
* [X86][BtVer2] Fix latency and resource cycles of AVX 256-bit zero-idioms.Andrea Di Biagio2018-09-211-4/+4
* [X86] Add scheduling tests for AVX1 256-bit zero-idioms. NFCAndrea Di Biagio2018-09-211-0/+84
* [X86][BtVer2] Fix WriteFShuffle256 schedule write info.Andrea Di Biagio2018-08-311-6/+6
* [X86] Fix skylake server scheduling info.Clement Courbet2018-06-111-60/+60
* [X86][BtVer2] Add support for all SUB/XOR 32/64 scalar instructions that shou...Simon Pilgrim2018-06-081-4/+4
* [CodeGen] assume max/default throughput for unspecified instructionsSanjay Patel2018-06-051-22/+22
* [X86][BtVer2] ADC/SBB take 2cy on an ALU pipe, not 1cy like ADD/SUBSimon Pilgrim2018-05-171-4/+4
* [X86][BtVer2] Fix MMX/YMM integer vector nt store schedulesSimon Pilgrim2018-05-141-1/+1
* [X86][BtVer2] Model ymm move as double pumped instructionsSimon Pilgrim2018-05-111-2/+2
* [X86] Split WriteF/WriteVec Move/Load/Store scheduler classes by vector widthSimon Pilgrim2018-05-111-2/+2
* [X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt schedule classesSimon Pilgrim2018-05-071-2/+2
* [X86][SandyBridge] Add (V)DPPS memory fold latenciesSimon Pilgrim2018-04-061-2/+2
* [X86][SandyBridge] SBWriteResPair +5cy Memory FoldsSimon Pilgrim2018-04-061-2/+2
* [X86] Remove some InstRWs for plain store instructions on Sandy Bridge.Craig Topper2018-04-051-18/+18
* [X86] Revert r329251-329254Craig Topper2018-04-051-18/+18
* [X86] Auto-generate complete checks. NFCCraig Topper2018-04-051-18/+18
* [X86] Correct the throughput for divide instructions in Sandy Bridge/Haswell/...Craig Topper2018-04-021-48/+48
* [X86][Btver2] Fix YMM BLENDPD/BLENDPS + UNPCKPD/UNPCKP instructions costsSimon Pilgrim2018-03-261-12/+12
* [X86][Btver2] Double the AGU and schedule pipe resources for YMMSimon Pilgrim2018-03-261-15/+15
* [X86][AVX1] Ensure we don't use later instruction sets in AVX1 schedule testsSimon Pilgrim2018-03-241-9/+9
* [X86] Correct the VROUND regular expressions in Znver1 scheduler model to acc...Craig Topper2018-03-221-4/+4
* [X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and VROUNDP...Craig Topper2018-03-221-4/+4
* [X86][SkylakeClient] Fix a bunch of instructions that were incorrectly assign...Craig Topper2018-03-221-15/+15
* [X86] Fix a bunch of overlapping regular expressions in the scheduler models.Craig Topper2018-03-181-1/+1
* [X86][SSE] Introduce Float/Vector WriteMove, WriteLoad and Writetore schedule...Simon Pilgrim2018-03-151-4/+4
* [X86][AVX] Use WriteFShuffleLd for broadcast reg-mem instructionsSimon Pilgrim2018-03-141-1/+1
* [X86][Btver2] Fix YMM shuffle, permute and permutevar scheduler costsSimon Pilgrim2018-03-141-13/+13
* [X86][SSE] Use WriteFShuffleLd for MOVDDUP/MOVSHDUP/MOVSLDUP reg-mem instruct...Simon Pilgrim2018-03-141-3/+3
* [X86][BTVER2] Fix throughput of YMM bitwise instructionsSimon Pilgrim2018-03-021-12/+12
* [X86] Allow int_x86_sse2_cvtps2dq and int_x86_avx_cvt_ps2dq_256 to select EVE...Craig Topper2018-02-241-1/+1
* [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the...Craig Topper2018-02-131-4/+4
* [X86][SSE] Don't chain shuffles together in schedule testsSimon Pilgrim2018-02-031-20/+38
* [X86] Add a DAG combine to combine (sext (setcc)) with VLXCraig Topper2018-01-091-10/+6
* Reapply "[X86] Flag BroadWell scheduler model as complete"Sanjoy Das2017-12-121-7/+7
* Revert "[X86] Flag BroadWell scheduler model as complete"Sanjoy Das2017-12-121-7/+7
* [X86] Flag BroadWell scheduler model as completeSimon Pilgrim2017-12-101-7/+7
* Regenerate some scheduling tests that got missedSimon Pilgrim2017-12-101-16/+16
* [X86] Fix bad regular expressions in the scheduler models. Question marks sho...Craig Topper2017-12-101-8/+8
* [X86][Haswell]: Updating the scheduling information for the Haswell subtarget.Gadi Haber2017-12-081-178/+178
* [X86][AVX] Regenerate vpmovm2*/vpmov*2m avx512 schedule testsSimon Pilgrim2017-12-061-4/+4
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-720/+720
* [X86][AVX] Add scheduling test for vmovntdq 256-bit storeSimon Pilgrim2017-11-141-0/+67
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