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authorSimon Pilgrim <llvm-dev@redking.me.uk>2018-04-06 11:00:51 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2018-04-06 11:00:51 +0000
commit8a83f16ccd089224e7e84c0a1524296fccf61419 (patch)
treed0808a41e9a7c61b8da4daa668f95106bcd7dec8 /llvm/test/CodeGen/X86/avx-schedule.ll
parentda8b71f292976eb64cb5a07d0ba8b5960cc3a973 (diff)
downloadbcm5719-llvm-8a83f16ccd089224e7e84c0a1524296fccf61419.tar.gz
bcm5719-llvm-8a83f16ccd089224e7e84c0a1524296fccf61419.zip
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds
As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
Diffstat (limited to 'llvm/test/CodeGen/X86/avx-schedule.ll')
-rw-r--r--llvm/test/CodeGen/X86/avx-schedule.ll4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/X86/avx-schedule.ll b/llvm/test/CodeGen/X86/avx-schedule.ll
index eff1d6cfd7e..26af928b099 100644
--- a/llvm/test/CodeGen/X86/avx-schedule.ll
+++ b/llvm/test/CodeGen/X86/avx-schedule.ll
@@ -1607,13 +1607,13 @@ define <8 x float> @test_dpps(<8 x float> %a0, <8 x float> %a1, <8 x float> *%a2
; GENERIC-LABEL: test_dpps:
; GENERIC: # %bb.0:
; GENERIC-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [12:2.00]
-; GENERIC-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
+; GENERIC-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
; SANDY-LABEL: test_dpps:
; SANDY: # %bb.0:
; SANDY-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 # sched: [12:2.00]
-; SANDY-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [7:1.00]
+; SANDY-NEXT: vdpps $7, (%rdi), %ymm0, %ymm0 # sched: [8:1.00]
; SANDY-NEXT: retq # sched: [1:1.00]
;
; HASWELL-LABEL: test_dpps:
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