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Raptor Computing Systems
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llvm
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test
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CodeGen
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X86
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2012-1-10-buildvector.ll
Commit message (
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Author
Age
Files
Lines
*
[CodeGen] Unify MBB reference format in both MIR and debug output
Francis Visoiu Mistrih
2017-12-04
1
-2
/
+2
*
[X86] Add a target-specific DAG combine to combine extract_subvector from all...
Craig Topper
2017-08-27
1
-1
/
+0
*
[X86] SET0 to use XMM registers where possible PR26018 PR32862
Dinar Temirbulatov
2017-07-27
1
-1
/
+1
*
[X86][SSE] Fix domains for VZEXT_LOAD type instructions
Simon Pilgrim
2016-12-15
1
-2
/
+2
*
[X86][SSE] Consistently set MOVD/MOVQ load/store/move instructions to integer...
Simon Pilgrim
2016-12-07
1
-1
/
+1
*
[X86] No need to avoid selecting AVX_SET0 for 256-bit integer types when only...
Craig Topper
2016-05-08
1
-1
/
+1
*
Make utils/update_llc_test_checks.py note that the assertions are
James Y Knight
2015-11-23
1
-0
/
+1
*
use update_llc_test_checks.py to tighten checking
Sanjay Patel
2015-04-03
1
-14
/
+14
*
[X86, AVX] fix zero-extending integer operand load patterns to use integer in...
Sanjay Patel
2015-03-31
1
-1
/
+1
*
[X86, AVX] try to lowerVectorShuffleAsElementInsertion() for all 256-bit vect...
Sanjay Patel
2015-03-31
1
-6
/
+7
*
[X86] Use vmovss to handle inserting an element into index 0 of a v8f32 vecto...
Craig Topper
2015-03-05
1
-1
/
+2
*
Update to more CodeGen tests to use CHECK-LABEL for labels corresponding to f...
Stephen Lin
2013-07-18
1
-2
/
+2
*
Fix a bug in the lowering of BUILD_VECTOR for AVX. SCALAR_TO_VECTOR does not ...
Nadav Rotem
2012-01-11
1
-2
/
+15
*
Fix a bug in the legalization of shuffle vectors. When we emulate shuffles us...
Nadav Rotem
2012-01-10
1
-0
/
+13