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authorSanjay Patel <spatel@rotateright.com>2015-03-31 16:32:11 +0000
committerSanjay Patel <spatel@rotateright.com>2015-03-31 16:32:11 +0000
commit2ae9943881389a83fdc043d5b8ebb7009d053158 (patch)
treed6b842ef6938f8fc8277faec8678e05ead752ec6 /llvm/test/CodeGen/X86/2012-1-10-buildvector.ll
parent0e1f11ffe0afd0604bbee218ce74b915c732b678 (diff)
downloadbcm5719-llvm-2ae9943881389a83fdc043d5b8ebb7009d053158.tar.gz
bcm5719-llvm-2ae9943881389a83fdc043d5b8ebb7009d053158.zip
[X86, AVX] try to lowerVectorShuffleAsElementInsertion() for all 256-bit vector sub-types
I suggested this change in D7898 (http://llvm.org/viewvc/llvm-project?view=revision&revision=231354) It improves the v4i64 case although not optimally. This AVX codegen: vmovq {{.*#+}} xmm0 = mem[0],zero vxorpd %ymm1, %ymm1, %ymm1 vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3] Becomes: vmovsd {{.*#+}} xmm0 = mem[0],zero Unfortunately, this doesn't completely solve PR22685. There are still at least 2 problems under here: We're not handling v32i8 / v16i16. We're not getting the FP / int domains right for instruction selection. But since this patch alone appears to do no harm, reduces code duplication, and helps v4i64, I'm submitting this patch ahead of fixing the above. Differential Revision: http://reviews.llvm.org/D8341 llvm-svn: 233704
Diffstat (limited to 'llvm/test/CodeGen/X86/2012-1-10-buildvector.ll')
-rw-r--r--llvm/test/CodeGen/X86/2012-1-10-buildvector.ll13
1 files changed, 7 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/X86/2012-1-10-buildvector.ll b/llvm/test/CodeGen/X86/2012-1-10-buildvector.ll
index a9b8cc6c62a..ece28bfb6c5 100644
--- a/llvm/test/CodeGen/X86/2012-1-10-buildvector.ll
+++ b/llvm/test/CodeGen/X86/2012-1-10-buildvector.ll
@@ -3,25 +3,26 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"
target triple = "i686-pc-win32"
-;CHECK-LABEL: bad_cast:
+; CHECK-LABEL: bad_cast:
define void @bad_cast() {
entry:
%vext.i = shufflevector <2 x i64> undef, <2 x i64> undef, <3 x i32> <i32 0, i32 1, i32 undef>
%vecinit8.i = shufflevector <3 x i64> zeroinitializer, <3 x i64> %vext.i, <3 x i32> <i32 0, i32 3, i32 4>
store <3 x i64> %vecinit8.i, <3 x i64>* undef, align 32
-;CHECK: ret
+; CHECK: ret
ret void
}
-;CHECK-LABEL: bad_insert:
+; CHECK-LABEL: bad_insert:
define void @bad_insert(i32 %t) {
entry:
-;CHECK: vxorps %ymm1, %ymm1, %ymm1
-;CHECK-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
+; CHECK: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT: vmovaps %ymm0
+; CHECK: ret
+
%v2 = insertelement <8 x i32> zeroinitializer, i32 %t, i32 0
store <8 x i32> %v2, <8 x i32> addrspace(1)* undef, align 32
-;CHECK: ret
ret void
}
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