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* Regenerate UXTB testsSimon Pilgrim2019-07-271-51/+112
| | | | llvm-svn: 367179
* ARM: convert ORR instructions to ADD where possible on Thumb.Tim Northover2018-06-201-2/+2
| | | | | | | | | | | | Thumb has more 16-bit encoding space dedicated to ADD than ORR, allowing both a 3-address encoding and a wider range of immediates. So, particularly when optimizing for code size (but it doesn't make things worse elsewhere) it's beneficial to select an OR operation to an ADD if we know overflow won't occur. This is made even better by LLVM's penchant for putting operations in canonical form by converting the other way. llvm-svn: 335119
* [ARM] Replace HasT2ExtractPack with HasDSPSam Parker2017-02-171-68/+52
| | | | | | | | | | | Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
* ARM: yet another round of ARM test clean upsSaleem Abdulrasool2014-04-031-2/+2
| | | | llvm-svn: 205586
* Add GPRPair Register class to ARM.Jakob Stoklund Olesen2012-10-261-2/+2
| | | | | | | | | Some instructions in ARM require 2 even-odd paired GPRs. This patch adds support for such register class. Patch by Weiming Zhao! llvm-svn: 166816
* Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor ↵Andrew Trick2011-04-131-2/+2
| | | | | | | | | | | | | | | | | | | | | latency. Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129421
* update tests for smarter BIC usageJim Grosbach2010-07-201-1/+1
| | | | llvm-svn: 108846
* PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas.Evan Cheng2010-06-291-25/+68
| | | | llvm-svn: 107122
* PR7458: Try commuting Thumb2 instruction operands to put them into 2-addressBob Wilson2010-06-241-1/+1
| | | | | | form so they can be narrowed to 16-bit instructions. llvm-svn: 106762
* Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/packJim Grosbach2010-05-051-1/+1
| | | | | | | instructions to subtarget features and update tests to reflect. PR5717. llvm-svn: 103136
* Drop the ".w" qualifier for t2UXTB16* instructions as there is no 16-bit versionJohnny Chen2010-03-041-10/+10
| | | | | | of either sxtb16 or uxtb16, and the unified syntax does not specify ".w". llvm-svn: 97760
* Convert to FileCheckJim Grosbach2009-11-171-2/+26
| | | | llvm-svn: 89007
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-091-1/+1
| | | | llvm-svn: 81293
* Add thumb2 sign / zero extend with rotate instructions.Evan Cheng2009-07-031-0/+74
llvm-svn: 74755
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