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authorAndrew Trick <atrick@apple.com>2011-04-13 00:38:32 +0000
committerAndrew Trick <atrick@apple.com>2011-04-13 00:38:32 +0000
commitb53a00d2cbc643d461ebd57e8f029f38631bfd34 (patch)
tree0bb4300556bfe91933aaf65004de971f1ac5d721 /llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
parent3137d3cb499af07c021f5a12dad1cd5418dd024f (diff)
downloadbcm5719-llvm-b53a00d2cbc643d461ebd57e8f029f38631bfd34.tar.gz
bcm5719-llvm-b53a00d2cbc643d461ebd57e8f029f38631bfd34.zip
Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129421
Diffstat (limited to 'llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll')
-rw-r--r--llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll b/llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
index 2074f98cb60..35914b16790 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-uxtb.ll
@@ -128,9 +128,9 @@ define i32 @test10(i32 %p0) {
; ARMv7M: test10
; ARMv7M: mov.w r1, #16253176
+; ARMv7M: mov.w r2, #458759
; ARMv7M: and.w r0, r1, r0, lsr #7
-; ARMv7M: mov.w r1, #458759
-; ARMv7M: and.w r1, r1, r0, lsr #5
+; ARMv7M: and.w r1, r2, r0, lsr #5
; ARMv7M: orrs r0, r1
%tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1]
%tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2]
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