| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands | David Green | 2019-09-03 | 1 | -8/+8 |
| * | [ARM] Generate 8.1-m CSINC, CSNEG and CSINV instructions. | David Green | 2019-09-03 | 1 | -35/+27 |
| * | [MVE] VMOVX patterns | David Green | 2019-08-28 | 1 | -346/+202 |
| * | [ARM] MVE vector for 64bit types | David Green | 2019-07-15 | 1 | -0/+250 |
| * | [ARM] MVE VRINT support | David Green | 2019-07-13 | 1 | -0/+177 |
| * | [ARM] MVE bitwise instruction patterns | David Green | 2019-07-04 | 1 | -1/+1 |
| * | [ARM] MVE: allow soft-float ABI to pass vector types. | Simon Tatham | 2019-07-02 | 1 | -2191/+1055 |
| * | [ARM] Mark math routines as non-legal for MVE | David Green | 2019-06-28 | 1 | -0/+2322 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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