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path: root/llvm/test/CodeGen/Thumb2/float-ops.ll
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* [ARM] Split large truncating MVE storesDavid Green2019-09-241-1/+1
* [ARM] Stop using scalar FP instructions in integer-only MVE mode.Simon Tatham2019-07-021-19/+24
* [Thumb] Teach ISel how to lower compares of AND bitmasks efficientlySjoerd Meijer2016-12-151-5/+5
* Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"James Molloy2016-11-031-6/+6
* [Thumb] Teach ISel how to lower compares of AND bitmasks efficientlyJames Molloy2016-11-031-6/+6
* Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"James Molloy2016-09-141-6/+6
* [Thumb] Teach ISel how to lower compares of AND bitmasks efficientlyJames Molloy2016-09-131-6/+6
* Revert r281215, it caused PR30358.Nico Weber2016-09-121-6/+6
* [Thumb] Teach ISel how to lower compares of AND bitmasks efficientlyJames Molloy2016-09-121-6/+6
* Revert "CodeGen: ensure that libcalls are always AAPCS CC"Saleem Abdulrasool2016-09-071-3/+2
* CodeGen: ensure that libcalls are always AAPCS CCSaleem Abdulrasool2016-09-061-2/+3
* ARMLoadStoreOptimizer: Fix errata 602117 handling and make testcase actually ...Matthias Braun2015-06-241-1/+1
* ARM: Thumb2 LDRD/STRD supports independent input/output regsMatthias Braun2015-06-031-4/+2
* Revert "ARM: Thumb2 LDRD/STRD supports independent input/output regs"Renato Golin2015-06-021-2/+4
* ARM: Thumb2 LDRD/STRD supports independent input/output regsMatthias Braun2015-06-011-4/+2
* Thumb2SizeReduction: Check the correct set of registers for LDMIA.Peter Collingbourne2015-05-051-1/+1
* [opaque pointer type] Add textual IR support for explicit type parameter to l...David Blaikie2015-02-271-2/+2
* [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)Oliver Stannard2014-10-011-6/+9
* [ARM] Enable DP copy, load and store instructions for FPv4-SPOliver Stannard2014-08-211-0/+290
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