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* [RISCV] Switch to the Machine SchedulerLuis Marques2019-09-171-4/+4
| | | | | | | | | Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
* Revert Patch from PhabricatorLuis Marques2019-09-171-4/+4
| | | | | | This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
* Patch from PhabricatorLuis Marques2019-09-171-4/+4
| | | | llvm-svn: 372092
* [RISCV][NFC] Add nounwind attribute to functions missing it in ↵Alex Bradbury2019-05-231-2/+2
| | | | | | | | test/CodeGen/RISCV r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives. llvm-svn: 361493
* [RISCV] Separate base from offset in lowerGlobalAddressSameer AbuAsal2018-05-171-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When lowering global address, lower the base as a TargetGlobal first then create an SDNode for the offset separately and chain it to the address calculation This optimization will create a DAG where the base address of a global access will be reused between different access. The offset can later be folded into the immediate part of the memory access instruction. With this optimization we generate: lui a0, %hi(s) addi a0, a0, %lo(s) ; shared base address. addi a1, zero, 20 ; 2 instructions per access. sw a1, 44(a0) addi a1, zero, 10 sw a1, 8(a0) addi a1, zero, 30 sw a1, 80(a0) Instead of: lui a0, %hi(s+44) ; 3 instructions per access. addi a1, zero, 20 sw a1, %lo(s+44)(a0) lui a0, %hi(s+8) addi a1, zero, 10 sw a1, %lo(s+8)(a0) lui a0, %hi(s+80) addi a1, zero, 30 sw a1, %lo(s+80)(a0) Which will save one instruction per access. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D46989 llvm-svn: 332641
* [RISCV] Implement isZextFreeAlex Bradbury2018-04-261-10/+7
| | | | | | | This returns true for 8-bit and 16-bit loads, allowing LBU/LHU to be selected and avoiding unnecessary masks. llvm-svn: 330943
* [RISCV] Add test case showing suboptimal codegen when loading unsigned ↵Alex Bradbury2018-04-261-0/+79
char/short Implementing isZextFree will allow lbu or lhu to be selected rather than lb+mask and lh+mask. llvm-svn: 330942
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