Commit message (Expand) | Author | Age | Files | Lines | |
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* | [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/R... | Alex Bradbury | 2019-05-23 | 1 | -30/+30 |
* | [RISCV] Introduce codegen patterns for instructions introduced in RV64I | Alex Bradbury | 2018-11-30 | 1 | -3/+156 |
* | [RISCV] Implement frame pointer elimination | Alex Bradbury | 2018-01-18 | 1 | -210/+0 |
* | [RISCV] Enable emission of alias instructions by default | Alex Bradbury | 2017-12-15 | 1 | -39/+39 |
* | [RISCV] Implement prolog and epilog insertion | Alex Bradbury | 2017-12-11 | 1 | -0/+210 |
* | [CodeGen] Unify MBB reference format in both MIR and debug output | Francis Visoiu Mistrih | 2017-12-04 | 1 | -30/+30 |
* | [RISCV] Use register X0 (ZERO) for constant 0 | Alex Bradbury | 2017-11-21 | 1 | -15/+4 |
* | [RISCV] Support and tests for a variety of additional LLVM IR constructs | Alex Bradbury | 2017-11-21 | 1 | -0/+296 |