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path: root/llvm/test/CodeGen/RISCV/div.ll
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* [RISCV] Switch to the Machine SchedulerLuis Marques2019-09-171-1/+1
* Revert Patch from PhabricatorLuis Marques2019-09-171-1/+1
* Patch from PhabricatorLuis Marques2019-09-171-1/+1
* [RISCV] Introduce codegen patterns for RV64M-only instructionsAlex Bradbury2019-01-121-0/+251
* [RISCV] Expand function call to "call" pseudoinstructionShiva Chen2018-04-251-36/+12
* [RISCV] Codegen support for the standard RV32M instruction set extensionAlex Bradbury2018-01-181-1/+92
* [RISCV] Implement frame pointer eliminationAlex Bradbury2018-01-181-38/+0
* [RISCV][NFC] Add nounwind to functions in div.ll and mul.llAlex Bradbury2018-01-181-10/+10
* [RISCV] Enable emission of alias instructions by defaultAlex Bradbury2017-12-151-20/+20
* [RISCV] Implement prolog and epilog insertionAlex Bradbury2017-12-111-0/+54
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-111-16/+16
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-10/+10
* [RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury2017-11-211-0/+134
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