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path: root/llvm/test/CodeGen/RISCV/blockaddress.ll
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* [RISCV] Switch to the Machine SchedulerLuis Marques2019-09-171-5/+5
* Revert Patch from PhabricatorLuis Marques2019-09-171-5/+5
* Patch from PhabricatorLuis Marques2019-09-171-5/+5
* [RISCV] Peephole optimisation for load/store of global values or constant add...Alex Bradbury2018-03-191-6/+5
* [RISCV] Implement frame pointer eliminationAlex Bradbury2018-01-181-3/+0
* [RISCV] Enable emission of alias instructions by defaultAlex Bradbury2017-12-151-2/+2
* [RISCV] Implement prolog and epilog insertionAlex Bradbury2017-12-111-2/+7
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-111-2/+2
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-1/+1
* [RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury2017-11-211-0/+28
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