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path: root/llvm/test/CodeGen/RISCV/atomic-rmw.ll
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* [RISCV] Regenerate remat.ll and atomic-rmw.ll after D43256Fangrui Song2019-06-151-2360/+2560
* [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/R...Alex Bradbury2019-05-161-60/+60
* [RISCV] Optimize emission of SELECT sequencesAlex Bradbury2019-03-221-400/+200
* [RISCV] Only mark fp as reserved if the function has a dedicated frame pointerAlex Bradbury2019-03-131-2400/+2400
* Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUIAna Pazos2019-01-251-1988/+1448
* [RISCV] Custom-legalise 32-bit variable shifts on RV64Alex Bradbury2019-01-251-220/+220
* [RISCV] Add codegen support for RV64AAlex Bradbury2019-01-171-0/+3017
* [RISCV][NFC] Add CHECK lines for atomic operations on RV64IAlex Bradbury2019-01-111-0/+4902
* [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32AAlex Bradbury2018-09-191-0/+4282
* [RISCV] Codegen support for atomic operations on RV32IAlex Bradbury2018-06-131-0/+6133
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