[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV

This is in preparation for emitting CFI directives.

llvm-svn: 360897

1 files changed, 60 insertions, 60 deletions

diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index c464fa61538..7fcf8b0b4ef 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -8,7 +8,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IA %s
 
-define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) {
+define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -74,7 +74,7 @@ define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) {
   ret i8 %1
 }
 
-define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) {
+define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i8_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -140,7 +140,7 @@ define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) {
   ret i8 %1
 }
 
-define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) {
+define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -206,7 +206,7 @@ define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) {
   ret i8 %1
 }
 
-define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) {
+define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i8_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -272,7 +272,7 @@ define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) {
   ret i8 %1
 }
 
-define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) {
+define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -668,7 +668,7 @@ define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind {
   ret i8 %1
 }
 
-define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) {
+define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -734,7 +734,7 @@ define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) {
   ret i8 %1
 }
 
-define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) {
+define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i8_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -800,7 +800,7 @@ define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) {
   ret i8 %1
 }
 
-define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) {
+define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -866,7 +866,7 @@ define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) {
   ret i8 %1
 }
 
-define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) {
+define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i8_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -932,7 +932,7 @@ define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) {
   ret i8 %1
 }
 
-define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) {
+define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1268,7 +1268,7 @@ define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind {
   ret i8 %1
 }
 
-define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) {
+define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i8_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1336,7 +1336,7 @@ define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) {
   ret i8 %1
 }
 
-define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) {
+define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i8_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1404,7 +1404,7 @@ define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) {
   ret i8 %1
 }
 
-define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) {
+define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i8_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1472,7 +1472,7 @@ define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) {
   ret i8 %1
 }
 
-define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) {
+define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i8_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -1540,7 +1540,7 @@ define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) {
   ret i8 %1
 }
 
-define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) {
+define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i8_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -4928,7 +4928,7 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind {
   ret i8 %1
 }
 
-define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) {
+define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i16_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -4996,7 +4996,7 @@ define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) {
   ret i16 %1
 }
 
-define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) {
+define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i16_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -5064,7 +5064,7 @@ define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) {
   ret i16 %1
 }
 
-define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) {
+define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i16_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -5132,7 +5132,7 @@ define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) {
   ret i16 %1
 }
 
-define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) {
+define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i16_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -5200,7 +5200,7 @@ define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) {
   ret i16 %1
 }
 
-define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) {
+define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i16_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -5608,7 +5608,7 @@ define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind {
   ret i16 %1
 }
 
-define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) {
+define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i16_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -5676,7 +5676,7 @@ define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) {
   ret i16 %1
 }
 
-define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) {
+define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i16_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -5744,7 +5744,7 @@ define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) {
   ret i16 %1
 }
 
-define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) {
+define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i16_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -5812,7 +5812,7 @@ define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) {
   ret i16 %1
 }
 
-define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) {
+define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i16_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -5880,7 +5880,7 @@ define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) {
   ret i16 %1
 }
 
-define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) {
+define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i16_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -6228,7 +6228,7 @@ define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind {
   ret i16 %1
 }
 
-define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) {
+define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i16_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -6298,7 +6298,7 @@ define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) {
   ret i16 %1
 }
 
-define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) {
+define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i16_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -6368,7 +6368,7 @@ define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) {
   ret i16 %1
 }
 
-define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) {
+define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i16_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -6438,7 +6438,7 @@ define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) {
   ret i16 %1
 }
 
-define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) {
+define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i16_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -6508,7 +6508,7 @@ define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) {
   ret i16 %1
 }
 
-define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) {
+define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i16_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10058,7 +10058,7 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind {
   ret i16 %1
 }
 
-define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) {
+define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i32_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10092,7 +10092,7 @@ define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) {
   ret i32 %1
 }
 
-define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) {
+define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i32_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10126,7 +10126,7 @@ define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) {
   ret i32 %1
 }
 
-define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) {
+define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i32_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10160,7 +10160,7 @@ define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) {
   ret i32 %1
 }
 
-define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) {
+define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i32_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10194,7 +10194,7 @@ define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) {
   ret i32 %1
 }
 
-define i32 @atomicrmw_xchg_i32_seq_cst(i32* %a, i32 %b) {
+define i32 @atomicrmw_xchg_i32_seq_cst(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i32_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10398,7 +10398,7 @@ define i32 @atomicrmw_add_i32_seq_cst(i32 *%a, i32 %b) nounwind {
   ret i32 %1
 }
 
-define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) {
+define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i32_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10434,7 +10434,7 @@ define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) {
   ret i32 %1
 }
 
-define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) {
+define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i32_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10470,7 +10470,7 @@ define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) {
   ret i32 %1
 }
 
-define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) {
+define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i32_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10506,7 +10506,7 @@ define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) {
   ret i32 %1
 }
 
-define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) {
+define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i32_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10542,7 +10542,7 @@ define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) {
   ret i32 %1
 }
 
-define i32 @atomicrmw_sub_i32_seq_cst(i32* %a, i32 %b) {
+define i32 @atomicrmw_sub_i32_seq_cst(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i32_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10748,7 +10748,7 @@ define i32 @atomicrmw_and_i32_seq_cst(i32 *%a, i32 %b) nounwind {
   ret i32 %1
 }
 
-define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) {
+define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i32_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10796,7 +10796,7 @@ define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) {
   ret i32 %1
 }
 
-define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) {
+define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i32_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10844,7 +10844,7 @@ define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) {
   ret i32 %1
 }
 
-define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) {
+define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i32_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10892,7 +10892,7 @@ define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) {
   ret i32 %1
 }
 
-define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) {
+define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i32_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -10940,7 +10940,7 @@ define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) {
   ret i32 %1
 }
 
-define i32 @atomicrmw_nand_i32_seq_cst(i32* %a, i32 %b) {
+define i32 @atomicrmw_nand_i32_seq_cst(i32* %a, i32 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i32_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -13148,7 +13148,7 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind {
   ret i32 %1
 }
 
-define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) {
+define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i64_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -13187,7 +13187,7 @@ define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) {
   ret i64 %1
 }
 
-define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) {
+define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i64_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -13226,7 +13226,7 @@ define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) {
   ret i64 %1
 }
 
-define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) {
+define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i64_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -13265,7 +13265,7 @@ define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) {
   ret i64 %1
 }
 
-define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) {
+define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i64_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -13304,7 +13304,7 @@ define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) {
   ret i64 %1
 }
 
-define i64 @atomicrmw_xchg_i64_seq_cst(i64* %a, i64 %b) {
+define i64 @atomicrmw_xchg_i64_seq_cst(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_xchg_i64_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -13538,7 +13538,7 @@ define i64 @atomicrmw_add_i64_seq_cst(i64 *%a, i64 %b) nounwind {
   ret i64 %1
 }
 
-define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) {
+define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i64_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -13578,7 +13578,7 @@ define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) {
   ret i64 %1
 }
 
-define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) {
+define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i64_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -13618,7 +13618,7 @@ define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) {
   ret i64 %1
 }
 
-define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) {
+define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i64_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -13658,7 +13658,7 @@ define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) {
   ret i64 %1
 }
 
-define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) {
+define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i64_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -13698,7 +13698,7 @@ define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) {
   ret i64 %1
 }
 
-define i64 @atomicrmw_sub_i64_seq_cst(i64* %a, i64 %b) {
+define i64 @atomicrmw_sub_i64_seq_cst(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_sub_i64_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -13933,7 +13933,7 @@ define i64 @atomicrmw_and_i64_seq_cst(i64 *%a, i64 %b) nounwind {
   ret i64 %1
 }
 
-define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) {
+define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i64_monotonic:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -13979,7 +13979,7 @@ define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) {
   ret i64 %1
 }
 
-define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) {
+define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i64_acquire:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -14025,7 +14025,7 @@ define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) {
   ret i64 %1
 }
 
-define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) {
+define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i64_release:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -14071,7 +14071,7 @@ define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) {
   ret i64 %1
 }
 
-define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) {
+define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i64_acq_rel:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
@@ -14117,7 +14117,7 @@ define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) {
   ret i64 %1
 }
 
-define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) {
+define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) nounwind {
 ; RV32I-LABEL: atomicrmw_nand_i64_seq_cst:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16