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path: root/llvm/test/CodeGen/RISCV/alu32.ll
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* [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensionsShiva Chen2019-08-061-2/+2
* [RISCV] Add patterns for RV64I SLLW/SRLW/SRAW instructionsAlex Bradbury2019-01-121-10/+3
* [RISCV] Add support for the various RISC-V FMA instruction variantsAlex Bradbury2018-12-131-3/+3
* [RISCV] Remove RV64I SLLW/SRLW/SRAW patterns and add new test casesAlex Bradbury2018-12-011-2/+9
* [TargetLowering][RISCV] Introduce isSExtCheaperThanZExt hook and implement fo...Alex Bradbury2018-11-301-6/+3
* [RISCV] Introduce codegen patterns for instructions introduced in RV64IAlex Bradbury2018-11-301-1/+110
* [RISCV] Expand codegen -> compression sanity checks and move to a single fileAlex Bradbury2018-04-181-42/+0
* [RISCV] Tablegen-driven Instruction Compression.Sameer AbuAsal2018-04-061-0/+42
* [RISCV] Implement frame pointer eliminationAlex Bradbury2018-01-181-133/+0
* [RISCV] Enable emission of alias instructions by defaultAlex Bradbury2017-12-151-19/+19
* [RISCV] Implement prolog and epilog insertionAlex Bradbury2017-12-111-0/+133
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-19/+19
* [RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury2017-11-211-0/+4
* [RISCV] Re-generate test/CodeGen/RISCV/alu32.ll using update_llc_test_checks.pyAlex Bradbury2017-11-091-38/+58
* [RISCV] Codegen support for materializing constantsAlex Bradbury2017-11-081-1/+0
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+163
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