| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | R600 -> AMDGPU rename | Tom Stellard | 2015-06-13 | 1 | -12/+0 |
| | | | | | llvm-svn: 239657 | ||||
| * | [opaque pointer type] Add textual IR support for explicit type parameter to ↵ | David Blaikie | 2015-02-27 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794 | ||||
| * | R600: Non vector only instruction can be scheduled on trans unit | Vincent Lejeune | 2013-09-04 | 1 | -1/+1 |
| | | | | | llvm-svn: 189980 | ||||
| * | Revert "R600: Non vector only instruction can be scheduled on trans unit" | Tom Stellard | 2013-07-31 | 1 | -1/+1 |
| | | | | | | | This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. llvm-svn: 187526 | ||||
| * | R600: Non vector only instruction can be scheduled on trans unit | Vincent Lejeune | 2013-07-31 | 1 | -1/+1 |
| | | | | | llvm-svn: 187514 | ||||
| * | R600: Prettier asmPrint of Alu | Vincent Lejeune | 2013-05-02 | 1 | -1/+2 |
| | | | | | llvm-svn: 180956 | ||||
| * | R600: Reorganize lit tests and document how they should be organized | Tom Stellard | 2013-04-19 | 1 | -0/+11 |
| llvm-svn: 179828 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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