bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	R600 -> AMDGPU rename	Tom Stellard	2015-06-13	1	-40/+0
\| \| \| \|	llvm-svn: 239657
*	R600: Enable vector fpow.	Tom Stellard	2014-02-04	1	-4/+25
\| \| \| \| \| \| \| \| \| \| \|	The OpenCL specs say: "The vector versions of the math functions operate component-wise. The description is per-component." Patch by: Jan Vesely Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 200773
*	R600: Use function inputs to represent data stored in gpr	Vincent Lejeune	2013-11-11	1	-8/+8
\| \| \| \|	llvm-svn: 194425
*	R600: Support schedule and packetization of trans-only inst	Vincent Lejeune	2013-06-29	1	-2/+2
\| \| \| \|	llvm-svn: 185268
*	R600: Schedule copy from phys register at beginning of block	Vincent Lejeune	2013-06-05	1	-1/+1
\| \| \| \| \| \|	It allows regalloc pass to remove them by trivially assigning associated reg llvm-svn: 183336
*	R600: use capital letter for PV channel	Vincent Lejeune	2013-06-03	1	-1/+1
\| \| \| \|	llvm-svn: 183107
*	R600: Use bottom up scheduling algorithm	Vincent Lejeune	2013-05-17	1	-1/+1
\| \| \| \|	llvm-svn: 182129
*	R600: Prettier asmPrint of Alu	Vincent Lejeune	2013-05-02	1	-3/+3
\| \| \| \|	llvm-svn: 180956
*	R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730	Michel Danzer	2013-03-22	1	-1/+1
\| \| \| \|	llvm-svn: 177736
*	Add R600 backend	Tom Stellard	2012-12-11	1	-0/+19
	A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915