| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | R600 -> AMDGPU rename | Tom Stellard | 2015-06-13 | 1 | -42/+0 |
| | | | | | llvm-svn: 239657 | ||||
| * | [opaque pointer type] Add textual IR support for explicit type parameter to ↵ | David Blaikie | 2015-02-27 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794 | ||||
| * | R600: Swizzle texture/export instructions | Vincent Lejeune | 2013-06-04 | 1 | -5/+5 |
| | | | | | llvm-svn: 183229 | ||||
| * | R600: Improve texture handling | Vincent Lejeune | 2013-05-17 | 1 | -16/+16 |
| | | | | | llvm-svn: 182125 | ||||
| * | R600: Rename 128 bit registers. | Vincent Lejeune | 2013-05-17 | 1 | -16/+16 |
| | | | | | | | | | | Almost all instructions that takes a 128 bits reg as input (fetch, export...) have the abilities to swizzle their argument and output. Instead of printing default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions print potentially optimized swizzles themselves. llvm-svn: 182124 | ||||
| * | R600: Add lit tests for texture sampling instruction selection. | Michel Danzer | 2013-02-14 | 1 | -0/+42 |
| Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175138 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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