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path: root/llvm/test/CodeGen/R600/literals.ll
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* R600 -> AMDGPU renameTom Stellard2015-06-131-64/+0
| | | | llvm-svn: 239657
* R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol ↵Tom Stellard2014-10-011-4/+4
| | | | | | table llvm-svn: 218776
* R600: Move code handling literal folding into R600ISelLowering.Vincent Lejeune2013-09-121-0/+16
| | | | llvm-svn: 190644
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-041-6/+8
| | | | llvm-svn: 189980
* R600: Enable folding of inline literals into REQ_SEQUENCE instructionsTom Stellard2013-08-161-0/+13
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188517
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-311-4/+2
| | | | | | This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. llvm-svn: 187526
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-311-2/+4
| | | | llvm-svn: 187514
* DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)FreeTom Stellard2013-07-231-166/+0
| | | | | | | This commit also implements these functions for R600 and removes a test case that was relying on the buggy behavior. llvm-svn: 187007
* R600: Use KCache for kernel argumentsTom Stellard2013-07-231-6/+6
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186918
* R600: Signed literals are 64bits wideVincent Lejeune2013-05-021-0/+165
| | | | llvm-svn: 180960
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-021-2/+4
| | | | llvm-svn: 180956
* Test case hygiene.Benjamin Kramer2013-03-091-1/+1
| | | | llvm-svn: 176772
* R600: Emit function name in the AsmPrinterTom Stellard2013-02-051-0/+2
| | | | | | | | Emitting the function name allows us to check for it in the FileCheck tests so we can make sure FileCheck is checking the output of the correct function. llvm-svn: 174392
* Add R600 backendTom Stellard2012-12-111-0/+30
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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