bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Expand)	Author	Age	Files	Lines
*	R600: Non vector only instruction can be scheduled on trans unit	Vincent Lejeune	2013-09-04	1	-7/+7
*	R600: Expand vector float operations for both SI and R600	Tom Stellard	2013-08-16	1	-22/+26
*	R600: Set scheduling preference to Sched::Source	Tom Stellard	2013-08-12	1	-1/+1
*	R600: Add 64-bit float load/store support	Tom Stellard	2013-08-01	1	-0/+10
*	Revert "R600: Non vector only instruction can be scheduled on trans unit"	Tom Stellard	2013-07-31	1	-1/+1
*	R600: Non vector only instruction can be scheduled on trans unit	Vincent Lejeune	2013-07-31	1	-1/+1
*	R600: Schedule copy from phys register at beginning of block	Vincent Lejeune	2013-06-05	1	-1/+1
*	R600: use capital letter for PV channel	Vincent Lejeune	2013-06-03	1	-1/+1
*	R600: Use bottom up scheduling algorithm	Vincent Lejeune	2013-05-17	1	-1/+1
*	R600: Prettier asmPrint of Alu	Vincent Lejeune	2013-05-02	1	-4/+4
*	R600: Reorganize lit tests and document how they should be organized	Tom Stellard	2013-04-19	1	-2/+17
*	Add R600 backend	Tom Stellard	2012-12-11	1	-0/+16
*	Revert "test/CodeGen/R600: Add some basic tests v6"	Tom Stellard	2012-07-16	1	-15/+0
*	test/CodeGen/R600: Add some basic tests v6	Tom Stellard	2012-07-16	1	-0/+15