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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-07-31 20:43:27 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-07-31 20:43:27 +0000 |
| commit | ca69a53bae802896a7c3705c52d81f4819ee62ab (patch) | |
| tree | 72b723840529d5c66b0d0290c53d7bc5729dc4f4 /llvm/test/CodeGen/R600/fadd.ll | |
| parent | 0ebf29d41f5e52b7f842468e4230361916abd370 (diff) | |
| download | bcm5719-llvm-ca69a53bae802896a7c3705c52d81f4819ee62ab.tar.gz bcm5719-llvm-ca69a53bae802896a7c3705c52d81f4819ee62ab.zip | |
Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.
llvm-svn: 187526
Diffstat (limited to 'llvm/test/CodeGen/R600/fadd.ll')
| -rw-r--r-- | llvm/test/CodeGen/R600/fadd.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/R600/fadd.ll b/llvm/test/CodeGen/R600/fadd.ll index 205715db946..9a672329e75 100644 --- a/llvm/test/CodeGen/R600/fadd.ll +++ b/llvm/test/CodeGen/R600/fadd.ll @@ -18,7 +18,7 @@ declare void @llvm.AMDGPU.store.output(float, i32) ; CHECK: @fadd_v4f32 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { |
