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* R600 -> AMDGPU renameTom Stellard2015-06-131-53/+0
| | | | llvm-svn: 239657
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
* R600/SI: Enable all tests that pass on VI without changesMarek Olsak2015-01-271-0/+1
| | | | llvm-svn: 227214
* DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N))Tim Northover2015-01-211-12/+10
| | | | | | | It can help with argument juggling on some targets, and is generally a good idea. llvm-svn: 226740
* Revert "DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N))"Tim Northover2015-01-211-10/+12
| | | | | | | | It hadn't gone through review yet, but was still on my local copy. This reverts commit r226663 llvm-svn: 226665
* DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N))Tim Northover2015-01-211-12/+10
| | | | llvm-svn: 226663
* R600/SI: Remove some redudant load testcases.Matt Arsenault2015-01-141-66/+0
| | | | | | | This reduces coverage for Evergreen, since the more complete tests have those run lines disabled. llvm-svn: 225927
* R600/SI: Add a stub GCNTargetMachineTom Stellard2015-01-061-1/+1
| | | | | | | | | | | | This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
* R600/SI: Add SIFoldOperands passTom Stellard2014-11-211-12/+9
| | | | | | | This pass attempts to fold the source operands of mov and copy instructions into their uses. llvm-svn: 222581
* R600/SI: Change all instruction assembly names to lowercase.Tom Stellard2014-11-051-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the format produced by the AMD proprietary driver. //==================================================================// // Shell script for converting .ll test cases: (Pass the .ll files you want to convert to this script as arguments). //==================================================================// ; This was necessary on my system so that A-Z in sed would match only ; upper case. I'm not sure why. export LC_ALL='C' TEST_FILES="$*" MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r` for f in $TEST_FILES; do # Check that there are SI tests: grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f if [ $? -eq 0 ]; then for match in $MATCHES; do sed -i -e "s/\([ :]$match\)/\L\1/" $f done # Try to get check lines with partial instruction names sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f fi done sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll //==================================================================// // Shell script for converting .td files (run this last) //==================================================================// export LC_ALL='C' sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td llvm-svn: 221350
* R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol ↵Tom Stellard2014-10-011-10/+10
| | | | | | table llvm-svn: 218776
* R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variantTom Stellard2014-08-111-6/+6
| | | | | | | This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. llvm-svn: 215399
* R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errorsTom Stellard2014-04-291-1/+1
| | | | | | | | | | | | | | | | SI_IF and SI_ELSE are terminators which also produce a value. For these instructions ISel always inserts a COPY to move their value to another basic block. This COPY ends up between SI_(IF|ELSE) and the S_BRANCH* instruction at the end of the block. This breaks MachineBasicBlock::getFirstTerminator() and also the machine verifier which assumes that terminators are grouped together at the end of blocks. To solve this we coalesce the copy away right after ISel to make sure there are no instructions in between terminators at the end of blocks. llvm-svn: 207591
* R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIRTom Stellard2014-04-181-3/+6
| | | | llvm-svn: 206541
* R600: Fix extloads from i8 / i16 to i64.Matt Arsenault2014-03-061-5/+72
| | | | | | | This appears to only be working for global loads. Private and local break for other reasons. llvm-svn: 203135
* R600/SI: Add support for i8 and i16 private loads/storesTom Stellard2014-01-221-6/+8
| | | | llvm-svn: 199823
* R600: Fix selection failure on EXTLOADMatt Arsenault2013-11-131-0/+51
llvm-svn: 194547
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