summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/PowerPC
Commit message (Collapse)AuthorAgeFilesLines
...
* [NFC][PowerPC] Modify the test case add_cmp.llKang Zhang2019-07-191-32/+12
| | | | llvm-svn: 366526
* [NFC][PowerPC] Add the test to test the pass block-placementKang Zhang2019-07-182-1/+318
| | | | llvm-svn: 366407
* [PEI] Don't re-allocate a pre-allocated stack protector slotFrancis Visoiu Mistrih2019-07-171-1/+3
| | | | | | | | | | | | | | | | | | | | | | The LocalStackSlotPass pre-allocates a stack protector and makes sure that it comes before the local variables on the stack. We need to make sure that later during PEI we don't re-allocate a new stack protector slot. If that happens, the new stack protector slot will end up being **after** the local variables that it should be protecting. Therefore, we would have two slots assigned for two different stack protectors, one at the top of the stack, and one at the bottom. Since PEI will overwrite the assigned slot for the stack protector, the load that is used to compare the value of the stack protector will use the slot assigned by PEI, which is wrong. For this, we need to check if the object is pre-allocated, and re-use that pre-allocated slot. Differential Revision: https://reviews.llvm.org/D64757 llvm-svn: 366371
* [CodeGen] Add stack protector tests where the guard gets re-assignedFrancis Visoiu Mistrih2019-07-171-0/+15
| | | | | | In preparation of a fix, add tests for multiple backends. llvm-svn: 366370
* PowerPC/SPE: Fix load/store handling for SPEJustin Hibbits2019-07-171-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Pointed out in a comment for D49754, register spilling will currently spill SPE registers at almost any offset. However, the instructions `evstdd` and `evldd` require a) 8-byte alignment, and b) a limit of 256 (unsigned) bytes from the base register, as the offset must fix into a 5-bit offset, which ranges from 0-31 (indexed in double-words). The update to the register spill test is taken partially from the test case shown in D49754. Additionally, pointed out by Kei Thomsen, globals will currently use evldd/evstdd, though the offset isn't known at compile time, so may exceed the 8-bit (unsigned) offset permitted. This fixes that as well, by forcing it to always use evlddx/evstddx when accessing globals. Part of the patch contributed by Kei Thomsen. Reviewers: nemanjai, hfinkel, joerg Subscribers: kbarton, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D54409 llvm-svn: 366318
* [PowerPC][HTM] Fix impossible reg-to-reg copy assert with ttest builtinJinsong Ji2019-07-161-0/+30
| | | | | | | | | | | | | | | | | | | | Summary: This is exposed by our internal testing. The reduced testcase will assert with "Impossible reg-to-reg copy" We can't use COPY to do 32-bit to 64-bit conversion. Reviewers: kbarton, hfinkel, nemanjai Reviewed By: hfinkel Subscribers: hiraditya, MaskRay, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64499 llvm-svn: 366255
* [NFC][PowerPC] Add test case for D64195Zi Xuan Wu2019-07-161-0/+106
| | | | llvm-svn: 366191
* [PowerPC] Support fp128 libcallsFangrui Song2019-07-151-0/+164
| | | | | | | | | | | | | On PowerPC, IEEE 754 quadruple-precision libcall names use "kf" instead of "tf". In libgcc, libgcc/config/rs6000/float128-sed converts TF names to KF names. This patch implements its 24 substitution rules. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D64282 llvm-svn: 366039
* [NFC][PowerPC] Add the test block-placement.mirKang Zhang2019-07-151-0/+217
| | | | llvm-svn: 366037
* [NFC][PowerPC] Added test for MachinePRE.Kai Luo2019-07-121-0/+141
| | | | llvm-svn: 365883
* [MachinePipeliner] Fix order for nodes with Anti dependence in same cycleJinsong Ji2019-07-121-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Problem exposed in PowerPC functional testing. We did not consider Anti dependence for nodes in same cycle, so we may end up generating bad machine code. eg: the reduced test won't verify. *** Bad machine code: Using an undefined physical register *** - function: lame_encode_buffer_interleaved - basic block: %bb.4 (0x4bde4e12928) - instruction: %29:gprc = ADDZE %27:gprc, implicit-def dead $carry, implicit $carry - operand 3: implicit $carry Reviewers: bcahoon, kparzysz, hfinkel Subscribers: MaskRay, wuzish, nemanjai, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64192 llvm-svn: 365859
* [PowerPC][NFC] Update testcase to avoid dead codeJinsong Ji2019-07-111-2/+2
| | | | | | | The original testcase might be optimized out due to dead code, update the testcase to avoid it. llvm-svn: 365810
* [NFC][PowerPC] Added test to track current behaviour of TailDupKai Luo2019-07-111-0/+73
| | | | llvm-svn: 365746
* Boilerplate for producing XCOFF object files from the PowerPC backend.Sean Fertile2019-07-091-0/+37
| | | | | | | | | | Stubs out a number of the classes needed to produce a new object file format (XCOFF) for the powerpc-aix target. For testing input is an empty module which produces an object file with just a file header. Differential Revision: https://reviews.llvm.org/D61694 llvm-svn: 365541
* [NFC][PowerPC] Added a test to show current codegen of MachinePREKai Luo2019-07-091-0/+55
| | | | llvm-svn: 365447
* [PowerPC][Peephole] Combine extsw and sldi after instruction selectionKai Luo2019-07-091-4/+130
| | | | | | | | | | | Summary: `extsw` and `sldi` are supposed to be combined if they are in the same BB in instruction selection phase. This patch handles the case where extsw and sldi are not in the same BB. Differential Revision: https://reviews.llvm.org/D63806 llvm-svn: 365430
* [MachinePipeliner] Fix Phi refers to Phi in same stage in 1st epilogueJinsong Ji2019-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This is exposed by functional testing on PowerPC. In some pipelined loops, Phi refer to phi did not get value defined by the Phi, hence getting wrong value later. As the comment mentioned, we should "use the value defined by the Phi, unless we're generating the firstepilog and the Phi refers to a Phi in a different stage.", so Phi refering to same stage Phi should use the value defined by the Phi here. Reviewers: bcahoon, hfinkel Reviewed By: hfinkel Subscribers: MaskRay, wuzish, nemanjai, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64035 llvm-svn: 365428
* [PowerPC][MachinePipeliner][NFC] Add a testcase for Phi bug.Jinsong Ji2019-07-091-0/+34
| | | | llvm-svn: 365427
* [PowerPC][NFC]Update testcases using script.Jinsong Ji2019-07-081-15/+31
| | | | llvm-svn: 365330
* [NFC][PowerPC] Add the test add_cmp.llKang Zhang2019-07-081-0/+76
| | | | llvm-svn: 365285
* [PowerPC] Move TOC save to prologue when profitableNemanja Ivanovic2019-07-053-11/+7
| | | | | | | | | | | | | | | | | | | | | The indirect call sequence on PPC requires that the TOC base register be saved prior to the indirect call and restored after the call since the indirect call may branch to a global entry point in another DSO which will update the TOC base. Over the last couple of years, we have improved this to: - be able to hoist TOC saves from loops (with changes to MachineLICM) - avoid multiple saves when one dominates the other[s] However, it is still possible to have multiple TOC saves dynamically in the execution path if there is no dominance relationship between them. This patch moves the TOC save to the prologue when one of the TOC saves is in a block that post-dominates entry (i.e. it cannot be avoided) or if it is in a block that is hotter than entry. Differential revision: https://reviews.llvm.org/D63803 llvm-svn: 365232
* [PowerPC] Support constraint code "ww"Fangrui Song2019-07-042-0/+21
| | | | | | | | | | | | | Summary: "ww" and "ws" are both constraint codes for VSX vector registers that hold scalar double data. "ww" is preferred for float while "ws" is preferred for double. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D64119 llvm-svn: 365106
* [PowerPC] Hardware Loop branch instruction's condition may not be icmp.Chen Zheng2019-07-041-0/+41
| | | | | | | This fixes pr42492. Differential Revision: https://reviews.llvm.org/D64124 llvm-svn: 365104
* [Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)Roman Lebedev2019-07-032-445/+446
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the backend part of [[ https://bugs.llvm.org/show_bug.cgi?id=42457 | PR42457 ]]. In middle-end, we'd want to prefer the form with two adds - D63992, but as this diff shows, not every target will prefer that pattern. Out of 4 targets for which i added tests all seem to be ok with inc-of-add for scalars, but only X86 prefer that same pattern for vectors. Here i'm adding a new TLI hook, always defaulting to the inc-of-add, but adding AArch64,ARM,PowerPC overrides to prefer inc-of-add only for scalars. Reviewers: spatel, RKSimon, efriedma, t.p.northover, hfinkel Reviewed By: efriedma Subscribers: nemanjai, javed.absar, kristof.beyls, kbarton, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64090 llvm-svn: 365010
* [PowerPC] exclude ICmpZero in LSR if icmp can be replaced in later hardware ↵Chen Zheng2019-07-037-70/+62
| | | | | | | | | loop. Differential Revision: https://reviews.llvm.org/D63477 llvm-svn: 364993
* [NFC][Codegen][X86][AArch64][ARM][PowerPC] Recommit: Add test coverage for ↵Roman Lebedev2019-07-022-0/+873
| | | | | | | | | | | "add-of-inc" vs "sub-of-not" I initially committed it with --check-prefix instead of --check-prefixes (again, shame on me, and utils/update_*.py not complaining!) and did not have a moment to understand the failure, so i reverted it initially in rL64939. llvm-svn: 364945
* Revert "[NFC][Codegen][X86][AArch64][ARM][PowerPC] Add test coverage for ↵Roman Lebedev2019-07-022-873/+0
| | | | | | | | | | "add-of-inc" vs "sub-of-not"" Some test failures i don't have a moment to investigate. This reverts commit r364930. llvm-svn: 364939
* [NFC][Codegen][X86][AArch64][ARM][PowerPC] Add test coverage for ↵Roman Lebedev2019-07-022-0/+873
| | | | | | | | | | "add-of-inc" vs "sub-of-not" As it is pointed out in https://reviews.llvm.org/D63992, before we get to pick canonical variant in middle-end we should ensure best codegen in backend. llvm-svn: 364930
* [PowerPC] Implement the areMemAccessesTriviallyDisjoint hookQingShan Zhang2019-07-029-90/+113
| | | | | | | | | After implemented this hook, we will model the memory dependency in the scheduling dependency graph more precise, and will have more opportunity to reorder the load/stores, as they didn't have the dependency at some condition Differential Revision: https://reviews.llvm.org/D63804 llvm-svn: 364886
* [UpdateTestChecks][PowerPC] Avoid empty string when scrubbing loop commentsJinsong Ji2019-07-011-53/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: SCRUB_LOOP_COMMENT_RE was introduced in https://reviews.llvm.org/D31285 This works for some loops. However, we may generate lines with loop comments only. And since we don't scrub leading white spaces, this will leave an empty line there, and FileCheck will complain it. eg: llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll:27:15: error: found empty check string with prefix 'CHECK:' ; CHECK-NEXT: This prevented us from using the `update_llc_test_checks.py` for quite some cases. We should still keep the comment token there, so that we can safely scrub the loop comment without breaking FileCheck. Reviewers: timshen, hfinkel, lebedev.ri, RKSimon Subscribers: nemanjai, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63957 llvm-svn: 364775
* Default to Secure PLT on PPC for musl libc.Brad Smith2019-06-281-0/+2
| | | | | | This matches the default settings of clang. llvm-svn: 364675
* [PowerPC][HTM] Fix disassembling buffer overflow for tabortdc and othersJinsong Ji2019-06-271-0/+20
| | | | | | | | | | | | | | | | | This was reported in https://bugs.llvm.org/show_bug.cgi?id=41751 llvm-mc aborted when disassembling tabortdc. This patch try to clean up TM related DAGs. * Fixes the problem by remove explicit output of cr0, and put it as implicit def. * Update int_ppc_tbegin pattern to accommodate the implicit def of cr0. * Update the TCHECK operand and int_ppc_tcheck accordingly. * Add some builtin test and disassembly tests. * Remove unused CRRC0/crrc0 Differential Revision: https://reviews.llvm.org/D61935 llvm-svn: 364544
* Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into ↵Clement Courbet2019-06-264-0/+522
| | | | | | | | | | | | | | opt pipeline." Breaks sanitizers: libFuzzer :: cxxstring.test libFuzzer :: memcmp.test libFuzzer :: recommended-dictionary.test libFuzzer :: strcmp.test libFuzzer :: value-profile-mem.test libFuzzer :: value-profile-strcmp.test llvm-svn: 364416
* [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline.Clement Courbet2019-06-264-522/+0
| | | | | | | | | This allows later passes (in particular InstCombine) to optimize more cases. One that's important to us is `memcmp(p, q, constant) < 0` and memcmp(p, q, constant) > 0. llvm-svn: 364412
* Teach the DAGCombine to fold this pattern(c1 and c2 is constant).QingShan Zhang2019-06-262-193/+80
| | | | | | | | | | | | | | | | | | // fold (sext (select cond, c1, c2)) -> (select cond, sext c1, sext c2) // fold (zext (select cond, c1, c2)) -> (select cond, zext c1, zext c2) // fold (aext (select cond, c1, c2)) -> (select cond, sext c1, sext c2) Sign extend the operands if it is any_extend, to keep the signess of the operands that, the other combine rule would apply. The any_extend is handled as zero extend for constants. i.e. t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0> t2: i64 = any_extend t1 --> t3: i64 = select t0, Constant:i64<-1>, Constant:i64<0> --> t4: i64 = sign_extend_inreg t3 Differential Revision: https://reviews.llvm.org/D63318 llvm-svn: 364382
* [NFC] Fix buildbot breaks due to r364375Nemanja Ivanovic2019-06-261-1/+1
| | | | | | | | For some reason, the update_llc_checks.py script produces checks for empty lines which cause failures. Corrected that to check for actual text produced by llc. llvm-svn: 364377
* [PowerPC][NFC] Add a TOC save test case prior to posting a related patchNemanja Ivanovic2019-06-261-0/+68
| | | | | | | | An upcoming patch will modify the behaviour with respect to saving the TOC in functions with indirect calls. Adding a test case so the patch will show the difference in codegen. llvm-svn: 364375
* [PowerPC] Mark FCOPYSIGN legal for FP vectorsNemanja Ivanovic2019-06-261-0/+27
| | | | | | | | | | This was just an omission in the back end. We have had the instructions for both single and double precision for a few HW generations, but never got around to legalizing these. Differential revision: https://reviews.llvm.org/D63634 llvm-svn: 364373
* [MachinePipeliner] Fix risky iterator usage R++, --RJinsong Ji2019-06-251-1/+1
| | | | | | | | | | | | | When we calculate MII, we use two loops, one with iterator R++ to check whether we can reserve the resource, then --R to move back the iterator to do reservation. This is risky, as R++, --R may not point to the same element at all. The can cause wrong MII. Differential Revision: https://reviews.llvm.org/D63536 llvm-svn: 364353
* [PowerPC][NFC]Add a test for MachinePipeliner bugJinsong Ji2019-06-251-0/+36
| | | | llvm-svn: 364350
* [DAGCombine] combineRepeatedFPDivisors - recognize -1.0 / X as a reciprocalSimon Pilgrim2019-06-251-0/+32
| | | | | | Fixes issue identified by @nemanjai (Nemanja Ivanovic) in D62963 / rL363040 - infinite loop due to GetNegatedExpression fighting combineRepeatedFPDivisors resulting in fneg(fdiv(x,splat)) -> fneg(fmul(x,1.0/splat)) -> fmul(x,-1.0/splat) -> fmul(x,(-1.0 * 1.0)/splat) ...... llvm-svn: 364326
* [PPC32] Support PLT calls for -msecure-plt -fpicFangrui Song2019-06-252-11/+35
| | | | | | | | | | | | | | | | | | | | Summary: In Secure PLT ABI, -fpic is similar to -fPIC. The differences are that: * -fpic stores the address of _GLOBAL_OFFSET_TABLE_ in r30, while -fPIC stores .got2+0x8000. * -fpic uses an addend of 0 for R_PPC_PLTREL24, while -fPIC uses 0x8000. Reviewers: hfinkel, jhibbits, joerg, nemanjai, spetrovic Reviewed By: jhibbits Subscribers: adalava, kbarton, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63563 llvm-svn: 364324
* [PowerPC] Emit XXSEL for vec_sel and code that has the same patternNemanja Ivanovic2019-06-251-0/+72
| | | | | | | | | | As pointed out in https://bugs.llvm.org/show_bug.cgi?id=41777 we do not emit a vector select even when the pretty much asks for one. This patch changes that. Differential revision: https://reviews.llvm.org/D61658 llvm-svn: 364289
* [CodeGen] Add missing vector type legalization for ctlz_zero_undefRoland Froese2019-06-241-13/+76
| | | | | | | | | Widen vector result type for ctlz_zero_undef and cttz_zero_undef the same as ctlz and cttz. Differential Revision: https://reviews.llvm.org/D63463 llvm-svn: 364221
* [PowerPC][UpdateTestChecks] powerpc- triple supportJinsong Ji2019-06-241-30/+33
| | | | | | | | | There are quite some old testcases with powerpc- triple, we should add this triple support so that we can update them with script. Differential Revision: https://reviews.llvm.org/D63723 llvm-svn: 364213
* Rename ExpandISelPseudo->FinalizeISel, delay register reservationMatt Arsenault2019-06-191-1/+1
| | | | | | | | | | | This allows targets to make more decisions about reserved registers after isel. For example, now it should be certain there are calls or stack objects in the frame or not, which could have been introduced by legalization. Patch by Matthias Braun llvm-svn: 363757
* [SelectionDAG] Legalize vaargs that require vector splittingSimon Pilgrim2019-06-181-0/+52
| | | | | | | | | | This adds vector splitting for vaarg instructions during type legalization Committed on behalf of @luke (Luke Lau) Differential Revision: https://reviews.llvm.org/D60762 llvm-svn: 363671
* [lit] Delete empty lines at the end of lit.local.cfg NFCFangrui Song2019-06-171-1/+0
| | | | llvm-svn: 363538
* Describe stack-id as an enumSander de Smalen2019-06-175-11/+11
| | | | | | | | | | | | | | | | | This patch changes MIR stack-id from an integer to an enum, and adds printing/parsing support for this in MIR files. The default stack-id '0' is now renamed to 'default'. This should make MIR tests that have stack objects with different stack-ids more descriptive. It also clarifies code operating on StackID. Reviewers: arsenm, thegameg, qcolombet Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D60137 llvm-svn: 363533
* PowerPC: Optimize SPE double parameter calling setupJustin Hibbits2019-06-171-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: SPE passes doubles the same as soft-float, in register pairs as i32 types. This is all handled by the target-independent layer. However, this is not optimal when splitting or reforming the doubles, as it pushes to the stack and loads from, on either side. For instance, to pass a double argument to a function, assuming the double value is in r5, the sequence currently looks like this: evstdd 5, X(1) lwz 3, X(1) lwz 4, X+4(1) Likewise, to form a double into r5 from args in r3 and r4: stw 3, X(1) stw 4, X+4(1) evldd 5, X(1) This optimizes the fence to use SPE instructions. Now, to pass a double to a function: mr 4, 5 evmergehi 3, 5, 5 And to form a double into r5 from args in r3 and r4: evmergelo 5, 3, 4 This is comparable to the way that gcc generates the double splits. This also fixes a bug with expanding builtins to libcalls, where the LowerCallTo() code path was generating intermediate illegal type nodes. Reviewers: nemanjai, hfinkel, joerg Subscribers: kbarton, jfb, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D54583 llvm-svn: 363526
OpenPOWER on IntegriCloud