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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2019-06-26 01:48:57 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2019-06-26 01:48:57 +0000 |
| commit | 8265e8ff3656d83bfb15447f396ec717c508256b (patch) | |
| tree | b833755c78b3ad952457af87a829c7471bfab797 /llvm/test/CodeGen/PowerPC | |
| parent | 174b4ff781a56b98d8f43454fbda834c5dab3cc2 (diff) | |
| download | bcm5719-llvm-8265e8ff3656d83bfb15447f396ec717c508256b.tar.gz bcm5719-llvm-8265e8ff3656d83bfb15447f396ec717c508256b.zip | |
[PowerPC] Mark FCOPYSIGN legal for FP vectors
This was just an omission in the back end. We have had the instructions for both
single and double precision for a few HW generations, but never got around to
legalizing these.
Differential revision: https://reviews.llvm.org/D63634
llvm-svn: 364373
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vector-copysign.ll | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/PowerPC/vector-copysign.ll b/llvm/test/CodeGen/PowerPC/vector-copysign.ll new file mode 100644 index 00000000000..107b4395803 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/vector-copysign.ll @@ -0,0 +1,27 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ +; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s +define dso_local <2 x double> @test(<2 x double> %a, <2 x double> %b) local_unnamed_addr { +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvcpsgndp v2, v3, v2 +; CHECK-NEXT: blr +entry: + %0 = tail call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b) + ret <2 x double> %0 +} + +define dso_local <4 x float> @test2(<4 x float> %a, <4 x float> %b) local_unnamed_addr { +; CHECK-LABEL: test2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xvcpsgnsp v2, v3, v2 +; CHECK-NEXT: blr +entry: + %0 = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b) + ret <4 x float> %0 +} + +declare <2 x double> @llvm.copysign.v2f64(<2 x double>, <2 x double>) +declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>) |
