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* [PowerPC] Combine ADD to ADDZEQingShan Zhang2018-09-071-0/+172
* [PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8QingShan Zhang2018-09-034-67/+67
* [PPC] Remove Darwin support from POWER backend.Kit Barton2018-08-28119-652/+557
* [PowerPC] Revert commit r339779Nemanja Ivanovic2018-08-272-100/+7
* [PowerPC] Recommit r340016 after fixing the reported issueNemanja Ivanovic2018-08-271-0/+17
* [PowerPC] Emit xscpsgndp instead of xxlor when copying floating point scalar ...Stefan Pintilie2018-08-245-14/+62
* [Exception Handling] Unwind tables are required for all functions that have a...Stefan Pintilie2018-08-241-0/+51
* [PowerPC] Change Test Options [NFC]Stefan Pintilie2018-08-243-750/+782
* Revert "[Exception Handling] Unwind tables are required for all functions tha...Stefan Pintilie2018-08-241-51/+0
* [Exception Handling] Unwind tables are required for all functions that have a...Stefan Pintilie2018-08-241-0/+51
* Temporarily Revert "[PowerPC] Generate Power9 extswsli extend sign and shift ...Eric Christopher2018-08-211-17/+0
* [PowerPC] Add a peephole post RA to transform the inst that fed by addQingShan Zhang2018-08-2018-107/+109
* [PowerPC] Generate lxsd instead of the ld->mtvsrd sequence for vector loadsStefan Pintilie2018-08-171-0/+274
* [PowerPC] Generate Power9 extswsli extend sign and shift immediate instructionNemanja Ivanovic2018-08-171-0/+17
* [SelectionDAG] Improve the legalisation lowering of UMULO.Eli Friedman2018-08-161-0/+177
* [PowerPC] Enhance the selection(ISD::VSELECT) of vector typeNemanja Ivanovic2018-08-151-5/+98
* [PowerPC] Don't run BV DAG Combine before legalization if it assumes legal typesNemanja Ivanovic2018-08-151-0/+55
* [SelectionDAG] try harder to convert funnel shift to rotateSanjay Patel2018-08-091-3/+1
* [PowerPC] Improve codegen for vector loads using scalar_to_vectorZaara Syeda2018-08-0811-219/+1444
* [PowerPC] Do not round values prior to converting to integerNemanja Ivanovic2018-08-021-204/+153
* [SelectionDAG] fix bug in translating funnel shift with non-power-of-2 typeSanjay Patel2018-08-012-40/+24
* [DAGCombiner] transform sub-of-shifted-signbit to addSanjay Patel2018-07-301-8/+8
* [AArch64, PowerPC, x86] add more signbit math tests; NFCSanjay Patel2018-07-271-7/+32
* [AArch64, PowerPC, x86] add more signbit math tests; NFCSanjay Patel2018-07-271-0/+28
* [DAGCombiner] fold 'not' with signbit mathSanjay Patel2018-07-271-13/+8
* [PowerPC] add more tests for signbit math; NFCSanjay Patel2018-07-271-0/+96
* [SelectionDAG] try to convert funnel shift directly to rotate if legalSanjay Patel2018-07-251-3/+1
* [AArch, PowerPC] add more tests for legal rotate ops; NFCSanjay Patel2018-07-251-4/+25
* [Power9] Code Cleanup - Remove needsAggressiveScheduling()Stefan Pintilie2018-07-1912-199/+164
* Introduce codegen for the Signal Processing EngineJustin Hibbits2018-07-185-10/+599
* [Intrinsics] define funnel shift IR intrinsics + DAG builder supportSanjay Patel2018-07-162-0/+485
* [DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)Sanjay Patel2018-07-153-12/+12
* [PowerPC] Materialize more constants with CR-field set in late peepholeNemanja Ivanovic2018-07-132-3/+422
* [PowerPC] [NFC] Update __float128 testsStefan Pintilie2018-07-129-1067/+1074
* [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm testsJoel E. Denny2018-07-114-13/+13
* [Power9] Add remaining __flaot128 builtin support for FMA round to oddStefan Pintilie2018-07-111-43/+54
* [Power9] Add __float128 builtins for Rounding OperationsStefan Pintilie2018-07-091-0/+76
* [Power9] [LLVM] Add __float128 support for trunc to double round to oddStefan Pintilie2018-07-091-0/+10
* [Power9] Add __float128 builtins for Round To OddStefan Pintilie2018-07-091-0/+82
* [Power9] Add __float128 support for compare operationsStefan Pintilie2018-07-091-0/+225
* [Power9] Add __float128 library call for fremStefan Pintilie2018-07-061-0/+14
* [Power9] Add lib calls for float128 operations with no equivalent PPC instruc...Lei Huang2018-07-051-1/+146
* [AArch64, PowerPC, x86] add tests for signbit bit hacks; NFCSanjay Patel2018-07-051-0/+151
* [Power9] Optimize codgen for conversions of int to float128Lei Huang2018-07-052-10/+136
* [Power9][NFC] add back-end tests for passing homogeneous fp128 aggregates by ...Lei Huang2018-07-051-3/+187
* [Power9] Add tests for passing float128 in VSX reg for non-homogenous aggregatesLei Huang2018-07-051-0/+206
* [Power9]Legalize and emit code for quad-precision convert from single-precisionLei Huang2018-07-052-27/+162
* [Power9] Implement float128 parameter passing and return valuesLei Huang2018-07-051-0/+268
* [Power9]Legalize and emit code for round & convert quad-precision valuesLei Huang2018-07-041-0/+154
* [PowerPC] Replace the Post RA List Scheduler with the Machine SchedulerStefan Pintilie2018-07-0476-482/+457
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