| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [PowerPC] Avoid scalarization of vector truncate | Roland Froese | 2019-02-11 | 1 | -258/+35 |
| | | | | | | | | | The PowerPC code generator currently scalarizes vector truncates that would fit in a vector register, resulting in vector extracts, scalar operations, and vector merges. This patch custom lowers a vector truncate that would fit in a register to a vector shuffle instead. Differential Revision: https://reviews.llvm.org/D56507 llvm-svn: 353724 | ||||
| * | [PowerPC] Add vector truncate test to prep for D56507 NFC | Roland Froese | 2019-02-06 | 1 | -0/+420 |
| llvm-svn: 353344 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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