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* [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0Kang Zhang2019-12-261-1/+1
| | | | | | | | | | | | | | | | | Summary: If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen` will set it as true for those instructions which has no match pattern. The instructions `MTLR` and `MFLR` don't set the hasSideEffects flag and don't have match pattern, so their hasSideEffects flag will be set true by `llvm-tblgen`. But in fact, we can use `[LR]` to model the two instructions, so they should not have SideEffects. This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D71390
* [PowerPC][NFC] Avoid checking non-relevant .cfi instructionsJinsong Ji2019-08-301-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This is brought up in https://reviews.llvm.org/D64662?id=209923#inline-599490 CFI information are non-relevant to quite some testcases, we should get rid of checking them when its unecessary. This patch avoid generating cfi info in testcases that are not testing prolog/epilog or exception handling. Reviewers: kbarton, hfinkel, nemanjai, #powerpc Reviewed By: hfinkel Subscribers: MaskRay, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67016 llvm-svn: 370505
* Re-commit "[PowerPC][NFC][MachinePipeliner] Add some regression testcases""Jinsong Ji2019-08-081-0/+89
| | | | | | Remove sms-cpy1.ll first while I investigate the problem. llvm-svn: 368318
* Temporarily Revert "[PowerPC][NFC][MachinePipeliner] Add some regression ↵Eric Christopher2019-08-031-89/+0
| | | | | | | | | | | | testcases" It's breaking a number of bots, e.g.: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap-msan/builds/13893/steps/check-llvm%20msan/logs/stdio This reverts commit r367732. llvm-svn: 367741
* [PowerPC][NFC][MachinePipeliner] Add some regression testcasesJinsong Ji2019-08-021-0/+89
Exposed by refactoring in https://reviews.llvm.org/D64665. llvm-svn: 367732
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