| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0 | Kang Zhang | 2019-12-26 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | Summary: If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen` will set it as true for those instructions which has no match pattern. The instructions `MTLR` and `MFLR` don't set the hasSideEffects flag and don't have match pattern, so their hasSideEffects flag will be set true by `llvm-tblgen`. But in fact, we can use `[LR]` to model the two instructions, so they should not have SideEffects. This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D71390 | ||||
| * | [PowerPC] Fix crash in peephole optimization | Nemanja Ivanovic | 2019-12-02 | 1 | -0/+56 |
| When converting reg+reg shifts to reg+imm rotates, we neglect to consider the CodeGenOnly versions of the 32-bit shift mnemonics. This means we produce a rotate with missing operands which causes a crash. Committing this fix without review since it is non-controversial that the list of mnemonics to consider should include the 64-bit aliases for the exact mnemonics. Fixes PR44183. | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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