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path: root/llvm/test/CodeGen/PowerPC/extract-and-store.ll
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* [MachineScheduler] Enable AA in PostRA Machine schedulerDavid Green2019-11-051-12/+12
| | | | | | | | | | | | This adds AA to Post-RA Machine Scheduling, allowing the pass more freedom when handling memory operations. My understanding is that this was just never done, not that it is inherently incorrect to do so. The older PostRA List scheduler already makes use of AA, it's just that the MI PostRA Scheduler was never taught to use it. Differential Revision: https://reviews.llvm.org/D69814
* [PowerPC] Clear the sideeffect bit for those instructions that didn't have ↵QingShan Zhang2019-10-301-6/+6
| | | | | | | | | | | | the match pattern If the instruction have match pattern, llvm-tblgen will infer the sideeffect bit from the match pattern and it works well. If not, the tblgen will set it as true that hurt the scheduling. PowerPC has some instructions that didn't specify the match pattern(i.e. LXSD etc), which is manually selected post-ra according to the register pressure. We need to clear the sideeffect flag for these instructions. Differential Revision: https://reviews.llvm.org/D69232
* [PowerPC] Implement the areMemAccessesTriviallyDisjoint hookQingShan Zhang2019-07-021-1/+1
| | | | | | | | | After implemented this hook, we will model the memory dependency in the scheduling dependency graph more precise, and will have more opportunity to reorder the load/stores, as they didn't have the dependency at some condition Differential Revision: https://reviews.llvm.org/D63804 llvm-svn: 364886
* [NFC] Test if commit access granted.Kai Luo2019-06-101-0/+1
| | | | llvm-svn: 362917
* [PowerPC][NFC] Add codegen test for consecutive stores of vector elementsNemanja Ivanovic2019-06-051-0/+535
| | | | | | | | | NFC commit of a test case in order for the subsequent review to show differences in codegen. Differential revision: https://reviews.llvm.org/D62843 llvm-svn: 362573
* [PowerPC][NFC] Fix typos in triplesJinsong Ji2019-05-141-4/+4
| | | | | | Found by bzEq (Kai Luo). llvm-svn: 360643
* [PowerPC] Exploit store instructions that store a single vector elementNemanja Ivanovic2019-01-241-76/+217
| | | | | | | | | | | This patch exploits the instructions that store a single element from a vector to preform a (store (extract_elt)). We already have code that does this with ISA 3.0 instructions that were added to handle i8/i16 types. However, we had never exploited the existing ones that handle f32/f64/i32/i64 types. Differential revision: https://reviews.llvm.org/D56175 llvm-svn: 352131
* [PowerPC][NFC] Add a test case for extract and store patternsNemanja Ivanovic2018-10-101-0/+339
An upcoming patch will change the codegen for these patterns. This test case is added now so that the patch can show the differences in codegen. llvm-svn: 344112
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