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* Adding -verify-machineinstrs option to PowerPC testsEhsan Amiri2016-08-031-2/+2
| | | | | | | | | | | Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
* [PowerPC] Clean up -mattr=+vsx tests to always specify -mcpuBill Schmidt2014-10-191-2/+2
| | | | | | | | | | | | | | We recently discovered an issue that reinforces what a good idea it is to always specify -mcpu in our code generation tests, particularly for -mattr=+vsx. This patch ensures that all tests that specify -mattr=+vsx also specify -mcpu=pwr7 or -mcpu=pwr8, as appropriate. Some of the uses of -mattr=+vsx added recently don't make much sense (when specified for -mtriple=powerpc-apple-darwin8 or -march=ppc32, for example). For cases like this I've just removed the extra VSX test commands; there's enough coverage without them. llvm-svn: 220173
* [PPC] Adjust some PowerPC tests to account for presence/absence of VSXBill Schmidt2014-10-171-1/+6
| | | | | | | | | | | Patch by Bill Seurer; committed on his behalf. These test cases generate slightly different code sequences when VSX is activated and thus fail. The update turns off VSX explicitly for the existing checks and then adds a second set of checks for most of them that test the VSX instruction output. llvm-svn: 220019
* llvm/test/CodeGen/PowerPC/2012-10-12-bitcast.ll: Try to fix failure on ↵NAKAMURA Takumi2012-10-121-1/+1
| | | | | | non-ppc hosts, to add -mattr=+altivec. llvm-svn: 165803
* Fix big-endian codegen bug in DAGTypeLegalizer::ExpandRes_BITCASTUlrich Weigand2012-10-121-0/+20
On PowerPC, a bitcast of <16 x i8> to i128 may run through a code path in ExpandRes_BITCAST that attempts to do an intermediate bitcast to a <4 x i32> vector, and then construct the Hi and Lo parts of the resulting i128 by pairing up two of those i32 vector elements each. The code already recognizes that on a big-endian system, the first two vector elements form the Hi part, and the final two vector elements form the Lo part (vice-versa from the little-endian situation). However, we also need to take endianness into account when forming each of those separate pairs: on a big-endian system, vector element 0 is the *high* part of the pair making up the Hi part of the result, and vector element 1 is the low part of the pair. The code currently always uses vector element 0 as the low part and vector element 1 as the high part, as is appropriate for little-endian platforms only. This patch fixes this by swapping the vector elements as they are paired up as appropriate. llvm-svn: 165802
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