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* [mips][micromips] Use call instructions with short delay slotsZoran Jovanovic2014-11-251-7/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D6338 llvm-svn: 222752
* [mips][microMIPS] This patch implements functionality in MIPS delay slotJozef Kolek2014-11-212-1/+20
| | | | | | | | | | | filler such as if delay slot filler have to put NOP instruction into the delay slot of microMIPS BEQ or BNE instruction which uses the register $0, then instead of emitting NOP this instruction is replaced by the corresponding microMIPS compact branch instruction, i.e. BEQZC or BNEZC. Differential Revision: http://reviews.llvm.org/D3566 llvm-svn: 222580
* [mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.Jozef Kolek2014-11-191-0/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D5800 llvm-svn: 222352
* [mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction.Jozef Kolek2014-11-191-0/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D5799 llvm-svn: 222351
* [mips][microMIPS] Implement SDBBP and RDHWR instructions.Jozef Kolek2014-11-191-0/+15
| | | | | | Differential Revision: http://reviews.llvm.org/D5240 llvm-svn: 222347
* First stage of call lowering for Mips fast-iselReed Kotler2014-11-131-0/+477
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This has most of what is needed for mips fast-isel call lowering for O32. What is missing I will add on the next patch because this patch is already too large. It should not be doing anything wrong but it will punt on some cases that it is basically capable of doing. The mechanism is there for parameters to be passed on the stack but I have not enabled it because it serves as a way for now to prevent some of the strange cases of O32 register passing that I have not fully checked yet and have some issues. The Mips O32 abi rules are very complicated as far how data is passed in floating and integer registers. However there is a way to think about this all very simply and this implementation reflects that. Basically, the ABI rules are written as if everything is passed on the stack and aligned as such. Once that is conceptually done, it is nearly trivial to reassign those locations to registers and then all the complexity disappears. So I have told tablegen that all the data is passed on the stack and during the lowering I fix this by assigning to registers as per the ABI doc. This has been my approach and you can line up what I did with the ABI document and see 1 to 1 what is going on. Test Plan: callabi.ll Reviewers: dsanders Reviewed By: dsanders Subscribers: jholewinski, echristo, ahatanak, llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D5714 llvm-svn: 221948
* [mips][micromips] Add predicate 'InMicroMips' at CodeGen patterns for ↵Zoran Jovanovic2014-11-121-0/+24
| | | | | | | | microMIPS instructions Differential Revision: http://reviews.llvm.org/D6198 llvm-svn: 221780
* [mips] Add preliminary support for the MIPS II target.Vasileios Kalintiris2014-11-111-0/+181
| | | | | | | | | | | | | | | | | | | Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
* [mips][microMIPS] Fix issue with delay slot filler and microMIPSZoran Jovanovic2014-11-101-0/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D6193 llvm-svn: 221612
* [mips] Fix sret arguments for N32/N64 which were accidentally broken in r221534.Daniel Sanders2014-11-101-0/+94
| | | | llvm-svn: 221604
* [mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit ↵Daniel Sanders2014-11-0719-140/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
* [mips] Tolerate the use of the %z inline asm operand modifier with ↵Toma Tabacu2014-11-061-0/+27
| | | | | | | | | | | | | | | | | | | | | | non-immediates. Summary: Currently, we give an error if %z is used with non-immediates, instead of continuing as if the %z isn't there. For example, you use the %z operand modifier along with the "Jr" constraints ("r" makes the operand a register, and "J" makes it an immediate, but only if its value is 0). In this case, you want the compiler to print "$0" if the inline asm input operand turns out to be an immediate zero and you want it to print the register containing the operand, if it's not. We give an error in the latter case, and we shouldn't (GCC also doesn't). Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6023 llvm-svn: 221453
* [mips] Add the following MIPS options that control gp-relative addressing ofSasa Stankovic2014-11-061-1/+1
| | | | | | | | | small data items: -mgpopt, -mlocal-sdata, -mextern-sdata. Implement gp-relative addressing for constants. Differential Revision: http://reviews.llvm.org/D4903 llvm-svn: 221450
* [mips64] Fix MIPS64 exception personality encodingPetar Jovanovic2014-11-051-5/+10
| | | | | | | | | | | Remove dynamic relocations of __gxx_personality_v0 from the .eh_frame. The MIPS64 follow-up of the MIPS32 fix (rL209907). Patch by Vladimir Stefanovic. Differential Revision: http://reviews.llvm.org/D6141 llvm-svn: 221408
* ps][microMIPS] Implement CodeGen support for ANDI16 instructionZoran Jovanovic2014-11-051-0/+25
| | | | llvm-svn: 221371
* ps][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructionsZoran Jovanovic2014-11-051-0/+44
| | | | llvm-svn: 221369
* Reverted revisions 221351, 221352 and 221353.Zoran Jovanovic2014-11-052-69/+0
| | | | llvm-svn: 221354
* [mips][microMIPS] Implement CodeGen support for ANDI16 instructionZoran Jovanovic2014-11-051-0/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D5797 llvm-svn: 221353
* [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructionsZoran Jovanovic2014-11-051-0/+44
| | | | | | Differential Revision: http://reviews.llvm.org/D5933 llvm-svn: 221352
* Revert "[mips] Add names and tests for the hardware registers"Rafael Espindola2014-11-041-2/+2
| | | | | | | | | | | | | This reverts commit r221299. The tests LLVM :: MC/Disassembler/Mips/mips32.txt LLVM :: MC/Disassembler/Mips/mips32_le.txt were failing. llvm-svn: 221307
* [mips] Add names and tests for the hardware registersVasileios Kalintiris2014-11-041-2/+2
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5763 llvm-svn: 221299
* [mips] For N32/N64, structs must be passed in the upper bits of a register.Daniel Sanders2014-10-241-0/+54
| | | | | | | | | | | | | | | | | | Summary: Most structs were fixed by r218451 but those of between >32-bits and <64-bits remained broken since they were not marked with [ASZ]ExtUpper. This patch fixes the remaining cases by using CCPromoteToUpperBitsInType<i64> on i64's in addition to i32 and smaller. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5963 llvm-svn: 220556
* [mips] Account for endianess when expanding BuildPairF64/ExtractElementF64 ↵Vasileios Kalintiris2014-10-161-67/+31
| | | | | | | | | | | | | | | | | | | | nodes. Summary: In order to support big endian targets for the BuildPairF64 nodes we just need to swap the low/high pair registers. Additionally, for the ExtractElementF64 nodes we have to calculate the correct stack offset with respect to the node's register/operand that we want to extract. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5753 llvm-svn: 219931
* [mips] Mark redundant instructions with a comment in ↵Daniel Sanders2014-10-131-2/+9
| | | | | | test/CodeGen/Mips/Fast-ISel/icmpa.ll. llvm-svn: 219605
* Add basic conditional branches in mips fast-iselReed Kotler2014-10-111-0/+34
| | | | | | | | | | | | | | | | | | Summary: Implement the most basic form of conditional branches in Mips fast-isel. Test Plan: br1.ll run 4 flavors of test-suite. mips32 r1/r2 and at -O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D5583 llvm-svn: 219556
* Implement floating point compare for mips fast-iselReed Kotler2014-10-101-0/+254
| | | | | | | | | | | | | | | | | | Summary: Expand SelectCmp to handle floating point compare Test Plan: fpcmpa.ll run 4 flavors of test-suite, mips32 r1/r2 O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D5567 llvm-svn: 219530
* implement integer compare in mips fast-iselReed Kotler2014-10-101-0/+203
| | | | | | | | | | | | | | | | | | Summary: implement SelectCmp (integer compare ) in mips fast-isel Test Plan: icmpa.ll also ran 4 test-suite flavors mips32 r1/r2 O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler, mcrosier Differential Revision: http://reviews.llvm.org/D5566 llvm-svn: 219518
* Implement floating point to integer conversion in mips fast-iselReed Kotler2014-10-101-0/+35
| | | | | | | | | | | | | | | | | | Summary: Add the ability to convert 64 or 32 bit floating point values to integer in mips fast-isel Test Plan: fpintconv.ll ran 4 flavors of test-suite with no errors, misp32 r1/r2 O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler, mcrosier Differential Revision: http://reviews.llvm.org/D5562 llvm-svn: 219511
* [mips] Return {f128} correctly for N32/N64.Daniel Sanders2014-10-071-0/+36
| | | | | | | | | | | | | | | | | Summary: According to the ABI documentation, f128 and {f128} should both be returned in $f0 and $f2. However, this doesn't match GCC's behaviour which is to return f128 in $f0 and $f2, but {f128} in $f0 and $f1. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5578 llvm-svn: 219196
* Add fptrunc to mips fast-selReed Kotler2014-10-011-0/+20
| | | | | | | | | | | | | | | | | | Summary: Implement conversion of 64 to 32 bit floating point numbers (fptrunc) in mips fast-isel Test Plan: fptrunc.ll checked also with 4 internal mips build bot flavors mip32r1/miprs32r2 and at -O0 and -O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: rfuhler Differential Revision: http://reviews.llvm.org/D5553 llvm-svn: 218785
* [mips] For indirect calls we don't need $gp to point to .got. Mips linkerSasa Stankovic2014-10-012-4/+15
| | | | | | | | | doesn't generate lazy binding stub for a function whose address is taken in the program. Differential Revision: http://reviews.llvm.org/D5067 llvm-svn: 218744
* Add numeric extend, trunctate to mips fast-iselReed Kotler2014-09-302-0/+200
| | | | | | | | | | | | | | | | | | | | | Summary: Add numeric extend, trunctate to mips fast-isel Reactivates D4827 Test Plan: fpext.ll loadstoreconv.ll Reviewers: dsanders Subscribers: mcrosier Differential Revision: http://reviews.llvm.org/D5251 llvm-svn: 218681
* Add soft-float to the key for the subtarget lookup in the TargetMachineEric Christopher2014-09-292-6/+51
| | | | | | | | | | | map, this makes sure that we can compile the same code for two different ABIs (hard and soft float) in the same module. Update one testcase accordingly (and fix some confusing naming) and add a new testcase as well with the ordering swapped which would highlight the problem. llvm-svn: 218632
* Add the first backend support for on demand subtarget creationEric Christopher2014-09-264-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | based on the Function. This is currently used to implement mips16 support in the mips backend via the existing module pass resetting the subtarget. Things to note: a) This involved running resetTargetOptions before creating a new subtarget so that code generation options like soft-float could be recognized when creating the new subtarget. This is to deal with initialization code in isel lowering that only paid attention to the initial value. b) Many of the existing testcases weren't using the soft-float feature correctly. I've corrected these based on the check values assuming that was the desired behavior. c) The mips port now pays attention to the target-cpu and target-features strings when generating code for a particular function. I've removed these from one function where the requested cpu and features didn't match the check lines in the testcase. llvm-svn: 218492
* [mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and ↵Daniel Sanders2014-09-251-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | handle struct's correctly on big-endian N32/N64 return values. Summary: The N32/N64 ABI's require that structs passed in registers are laid out such that spilling the register with 'sd' places the struct at the lowest address. For little endian this is trivial but for big-endian it requires that structs are shifted into the upper bits of the register. We also require that structs passed in registers have the 'inreg' attribute for big-endian N32/N64 to work correctly. This is because the tablegen-erated calling convention implementation only has access to the lowered form of struct arguments (one or more integers of up to 64-bits each) and is unable to determine the original type. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5286 llvm-svn: 218451
* Add mips32 r1 to the list of supported targets for Mips fast-iselReed Kotler2014-09-156-9/+35
| | | | | | | | | | | | | | | | | | | | | Summary: Expand list of supported targets for Mips to include mips32 r1. Previously it only include r2. More patches are coming where there is a difference but in the current patches as pushed upstream, r1 and r2 are equivalent. Test Plan: simplestorefp1.ll add new build bots at mips to test this flavor at both -O0 and -O2 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5306 llvm-svn: 217821
* Replace -use-init-array with -use-ctors.Rafael Espindola2014-09-021-1/+1
| | | | | | | | | | | | | We have been using .init-array for most systems for quiet some time, but tools like llc are still defaulting to .ctors because the old option was never changed. This patch makes llc default to .init-array and changes the option to be -use-ctors. Clang is not affected by this. It has its own fancier logic. llvm-svn: 216905
* [mips] Don't use odd-numbered float registers for double arguments for fastccSasa Stankovic2014-08-221-0/+82
| | | | | | | | calling convention if FP is 64-bit and +nooddspreg is used. Differential Revision: http://reviews.llvm.org/D4981.diff llvm-svn: 216262
* Fix fmul combines with constant splat vectorsMatt Arsenault2014-08-161-6/+4
| | | | | | Fixes things like fmul x, 2 -> fadd x, x llvm-svn: 215820
* [mips] Improve robustness of some tests.Toma Tabacu2014-08-147-65/+65
| | | | | | | | | | | | | | | | | Summary: This is done by removing some hardcoded registers like $at or expecting a single digit register to be selected. Contains work done by Matheus Almeida. Reviewers: matheusalmeida, dsanders Reviewed By: dsanders Subscribers: tomatabacu Differential Revision: http://reviews.llvm.org/D4227 llvm-svn: 215640
* Add support for scalarizing cttz_zero_undefPetar Jovanovic2014-08-101-0/+37
| | | | | | | | | Follow up to r214266. Add missing case in ScalarizeVectorResult() for cttz_zero_undef. Differential Revision: http://reviews.llvm.org/D4813 llvm-svn: 215330
* [mips] Invert the abicalls feature bit to be noabicalls so that it's ↵Daniel Sanders2014-08-081-13/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | possible for -mno-abicalls to take effect. Also added the testcase that should have been in r215194. This behaviour has surprised me a few times now. The problem is that the generated MipsSubtarget::ParseSubtargetFeatures() contains code like this: if ((Bits & Mips::FeatureABICalls) != 0) IsABICalls = true; so '-abicalls' means 'leave it at the default' and '+abicalls' means 'set it to true'. In this case, (and the similar -modd-spreg case) I'd like the code to be IsABICalls = (Bits & Mips::FeatureABICalls) != 0; or possibly: if ((Bits & Mips::FeatureABICalls) != 0) IsABICalls = true; else IsABICalls = false; and preferably arrange for 'Bits & Mips::FeatureABICalls' to be true by default (on some triples). llvm-svn: 215211
* [mips] Remove reason for XFAIL from a test that isn't actually XFAILed.Daniel Sanders2014-08-081-3/+0
| | | | llvm-svn: 215201
* fix materialization of one bit constants and global values which are ↵Reed Kotler2014-08-071-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | accessed through a base GOT entry. Summary: get tip of tree mips fast-isel to pass test-suite Two bugs were fixed: 1) one bit booleans were treated as 1 bit signed integers and so the literal '1' could become sign extended. 2) mips uses got for pic but in certain cases, as with string constants for example, many items can be referenced from the same got entry and this case was not handled properly. Test Plan: test-suite Reviewers: dsanders Reviewed By: dsanders Subscribers: mcrosier Differential Revision: http://reviews.llvm.org/D4801 llvm-svn: 215155
* llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll: Add explicit ↵NAKAMURA Takumi2014-08-011-4/+4
| | | | | | -mtriple=(mips|mipsel)-linux on 4 lines. llvm-svn: 214578
* [mips][PR19612] Fix va_arg for big-endian mode.Daniel Sanders2014-08-012-9/+1117
| | | | | | | | | | | | | | | | | | Summary: Big-endian mode was not correctly adjusting the offset for types smaller than an ABI slot. Fixes PR19612 Reviewers: dsanders Reviewed By: dsanders Subscribers: sstankovic, llvm-commits Differential Revision: http://reviews.llvm.org/D4556 llvm-svn: 214493
* Add support for scalarizing ctlz_zero_undefPetar Jovanovic2014-07-301-0/+19
| | | | | | | | | Fix the missing case in ScalarizeVectorResult() that was exposed with libclcore.bc in Android. Differential Revision: http://reviews.llvm.org/D4645 llvm-svn: 214266
* [mips] Don't use odd-numbered single precision registers for fastcc callingSasa Stankovic2014-07-291-0/+84
| | | | | | | | convention if -mno-odd-spreg is used. Differential Revision: http://reviews.llvm.org/D4682 llvm-svn: 214180
* [SDAG] Introduce a combined set to the DAG combiner which tracks nodesChandler Carruth2014-07-241-21/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | which have successfully round-tripped through the combine phase, and use this to ensure all operands to DAG nodes are visited by the combiner, even if they are only added during the combine phase. This is critical to have the combiner reach nodes that are *introduced* during combining. Previously these would sometimes be visited and sometimes not be visited based on whether they happened to end up on the worklist or not. Now we always run them through the combiner. This fixes quite a few bad codegen test cases lurking in the suite while also being more principled. Among these, the TLS codegeneration is particularly exciting for programs that have this in the critical path like TSan-instrumented binaries (although I think they engineer to use a different TLS that is faster anyways). I've tried to check for compile-time regressions here by running llc over a merged (but not LTO-ed) clang bitcode file and observed at most a 3% slowdown in llc. Given that this is essentially a worst case (none of opt or clang are running at this phase) I think this is tolerable. The actual LTO case should be even less costly, and the cost in normal compilation should be negligible. With this combining logic, it is possible to re-legalize as we combine which is necessary to implement PSHUFB formation on x86 as a post-legalize DAG combine (my ultimate goal). Differential Revision: http://reviews.llvm.org/D4638 llvm-svn: 213898
* [mips] Fix two patterns that select i32's (for MIPS32r6) / i64's (for MIPS64r6)Sasa Stankovic2014-07-221-0/+74
| | | | | | | | | | from setne comparison with an i32. The patterns that are fixed: * (select (i32 (setne i32, immZExt16)), i32, i32) (for MIPS32r6) * (select (i32 (setne i32, immZExt16)), i64, i64) (for MIPS64r6) llvm-svn: 213653
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