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* Add logical ops to Mips fast-iselReed Kotler2015-03-091-0/+605
| | | | | | | | | | | | | | | | | | | | | | Summary: Code is mostly copied from AArch64 port and modified where needed for Mips. This handles the "non" legal cases of logical ops. Legal cases are handled by tablegen patterns. Test Plan: Make check test logopm.ll All of test-suite passes at O0/O2 and mips32 r1/r2 with this new change. Reviewers: dsanders Reviewed By: dsanders Subscribers: echristo, llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D6599 llvm-svn: 231665
* [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generatorJozef Kolek2015-03-042-0/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D7609 llvm-svn: 231249
* Drop the "eh_" from eh_func_begin and eh_func_end.Rafael Espindola2015-03-041-1/+1
| | | | | | They will be used for more than eh tables. llvm-svn: 231185
* [mips] Optimize conditional moves where RHS is zero.Vasileios Kalintiris2015-03-021-175/+127
| | | | | | | | | | | | | Summary: When the RHS of a conditional move node is zero, we can utilize the $zero register by inverting the conditional move instruction and by swapping the order of its True/False operands. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D7945 llvm-svn: 230956
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-27268-3546/+3546
| | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-2741-358/+358
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | getelementptr instruction One of several parallel first steps to remove the target type of pointers, replacing them with a single opaque pointer type. This adds an explicit type parameter to the gep instruction so that when the first parameter becomes an opaque pointer type, the type to gep through is still available to the instructions. * This doesn't modify gep operators, only instructions (operators will be handled separately) * Textual IR changes only. Bitcode (including upgrade) and changing the in-memory representation will be in separate changes. * geps of vectors are transformed as: getelementptr <4 x float*> %x, ... ->getelementptr float, <4 x float*> %x, ... Then, once the opaque pointer type is introduced, this will ultimately look like: getelementptr float, <4 x ptr> %x with the unambiguous interpretation that it is a vector of pointers to float. * address spaces remain on the pointer, not the type: getelementptr float addrspace(1)* %x ->getelementptr float, float addrspace(1)* %x Then, eventually: getelementptr float, ptr addrspace(1) %x Importantly, the massive amount of test case churn has been automated by same crappy python code. I had to manually update a few test cases that wouldn't fit the script's model (r228970,r229196,r229197,r229198). The python script just massages stdin and writes the result to stdout, I then wrapped that in a shell script to handle replacing files, then using the usual find+xargs to migrate all the files. update.py: import fileinput import sys import re ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))") def conv(match, line): if not match: return line line = match.groups()[0] if len(match.groups()[5]) == 0: line += match.groups()[2] line += match.groups()[3] line += ", " line += match.groups()[1] line += "\n" return line for line in sys.stdin: if line.find("getelementptr ") == line.find("getelementptr inbounds"): if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("): line = conv(re.match(ibrep, line), line) elif line.find("getelementptr ") != line.find("getelementptr ("): line = conv(re.match(normrep, line), line) sys.stdout.write(line) apply.sh: for name in "$@" do python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name" rm -f "$name.tmp" done The actual commands: From llvm/src: find test/ -name *.ll | xargs ./apply.sh From llvm/src/tools/clang: find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}" From llvm/src/tools/polly: find test/ -name *.ll | xargs ./apply.sh After that, check-all (with llvm, clang, clang-tools-extra, lld, compiler-rt, and polly all checked out). The extra 'rm' in the apply.sh script is due to a few files in clang's test suite using interesting unicode stuff that my python script was throwing exceptions on. None of those files needed to be migrated, so it seemed sufficient to ignore those cases. Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7636 llvm-svn: 230786
* Change the fast-isel-abort option from bool to int to enable "levels"Mehdi Amini2015-02-2716-39/+39
| | | | | | | | | | | | | | | | | | | | | | | Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 230775
* Centralize handling of the eh_begin and eh_end labels.Rafael Espindola2015-02-271-1/+3
| | | | | | | | | | This removes a bit of duplicated code and more importantly, remembers the labels so that they don't need to be looked up by name. This in turn allows for any name to be used and avoids a crash if the name we wanted was already taken. llvm-svn: 230772
* [mips][microMIPS] Change register class for GP registerZoran Jovanovic2015-02-271-0/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D7934 llvm-svn: 230760
* [mips] Account for constant-zero operands in ADDE nodes.Vasileios Kalintiris2015-02-271-0/+35
| | | | | | | | | | | | | | | Summary: We identify the cases where the operand to an ADDE node is a constant zero. In such cases, we can avoid generating an extra ADDu instruction disguised as an identity move alias (ie. addu $r, $r, 0 --> move $r, $r). Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7906 llvm-svn: 230742
* Fix justify error for small structures in varargs for MIPS64BEPetar Jovanovic2015-02-263-0/+592
| | | | | | | | | | | | | | | There was a problem when passing structures as variable arguments. The structures smaller than 64 bit were not left justified on MIPS64 big endian. This is now fixed by shifting the value to make it left- justified when appropriate. This fixes the bug http://llvm.org/bugs/show_bug.cgi?id=21608 Patch by Aleksandar Beserminji. Differential Revision: http://reviews.llvm.org/D7881 llvm-svn: 230657
* Replace obsolete -mattr=n64 command line option with -target-abi=n64. No ↵Vladimir Medic2015-02-2615-35/+35
| | | | | | functional changes. llvm-svn: 230628
* [MIPS]Multiple and add instructions for Mips are currently available in ↵Vladimir Medic2015-02-251-32/+32
| | | | | | mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files. llvm-svn: 230500
* Replace obsolete -mattr=n64 command line option with -target-abi=n64. No ↵Vladimir Medic2015-02-251-6/+6
| | | | | | functional changes. llvm-svn: 230482
* Beginning of alloca implementation for Mips fast-iselReed Kotler2015-02-241-0/+64
| | | | | | | | | | | | | | | | Summary: Begin to add various address modes; including alloca. Test Plan: Make sure there are no regressions in test-suite at O0/02 in mips32r1/r2 Reviewers: dsanders Reviewed By: dsanders Subscribers: echristo, rfuhler, llvm-commits Differential Revision: http://reviews.llvm.org/D6426 llvm-svn: 230300
* [mips] Honour -mno-odd-spreg for vector insert/extract when MSA is enabled.Daniel Sanders2015-02-231-0/+131
| | | | | | | | | | | | | | | | | | | Summary: -mno-odd-spreg prohibits the use of odd-numbered single-precision floating point registers. However, vector insert/extract was still using them when manipulating the subregisters of an MSA register. Fixed this by ensuring that insertion/extraction is only performed on even-numbered vector registers when -mno-odd-spreg is given. Reviewers: vmedic, sstankovic Reviewed By: sstankovic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7672 llvm-svn: 230235
* Reversed revision 229706. The reason is regression, which is caused by theJozef Kolek2015-02-202-36/+0
| | | | | | | | usage of instruction ADDU16 by CodeGen. For this instruction an improper register is allocated, i.e. the register that is not from register set defined for the instruction. llvm-svn: 230053
* Revert r229944: EH: Prune unreachable resume instructions during Dwarf EH ↵Chandler Carruth2015-02-201-1/+0
| | | | | | | | | preparation This doesn't pass 'ninja check-llvm' for me. Lots of tests, including the ones updated, fail with crashes and other explosions. llvm-svn: 229952
* EH: Prune unreachable resume instructions during Dwarf EH preparationReid Kleckner2015-02-201-0/+1
| | | | | | | | | | | | | | | | | Today a simple function that only catches exceptions and doesn't run destructor cleanups ends up containing a dead call to _Unwind_Resume (PR20300). We can't remove these dead resume instructions during normal optimization because inlining might introduce additional landingpads that do have cleanups to run. Instead we can do this during EH preparation, which is guaranteed to run after inlining. Fixes PR20300. Reviewers: majnemer Differential Revision: http://reviews.llvm.org/D7744 llvm-svn: 229944
* [mips][microMIPS] Make usage of AND16, OR16 and XOR16 by code generatorJozef Kolek2015-02-193-0/+54
| | | | | | Differential Revision: http://reviews.llvm.org/D7611 llvm-svn: 229845
* [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generatorJozef Kolek2015-02-182-0/+36
| | | | | | Differential Revision: http://reviews.llvm.org/D7609 llvm-svn: 229706
* [mips] Add backend support for Mips32r[35] and Mips64r[35].Daniel Sanders2015-02-1817-103/+245
| | | | | | | | | | | | | | | | | Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
* [mips] Avoid redundant sign extension of the result of binary bitwise ↵Vasileios Kalintiris2015-02-183-13/+3
| | | | | | | | | | | | instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7581 llvm-svn: 229675
* [mips][microMIPS] Delay slot filler: Replace the microMIPS JR with the JRCJozef Kolek2015-02-133-6/+14
| | | | | | | | | | | This patch adds functionality in MIPS delay slot filler such as if delay slot filler have to put NOP instruction into the delay slot of microMIPS JR instruction, then instead of emitting NOP this instruction is replaced by compact jump instruction JRC. Differential Revision: http://reviews.llvm.org/D7522 llvm-svn: 229128
* Add bulk of returning of values to Mips fast-iselReed Kotler2015-02-121-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Implement the bulk of returning values in Mips fast-isel Test Plan: reatabi.ll Passes test-suite at -O0,-O2 and with mips32r2 and mips32r1. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D5920 llvm-svn: 228958
* Fix makeLibCall argument (signed) in SoftenFloatRes_XINT_TO_FP functionPetar Jovanovic2015-02-101-0/+15
| | | | | | | | | | | | | | The isSigned argument of makeLibCall function was hard-coded to false (unsigned). This caused zero extension on MIPS64 soft float. As the result SingleSource/Benchmarks/Stanford/FloatMM test and SingleSource/UnitTests/2005-07-17-INT-To-FP test failed. The solution was to use the proper argument. Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D7292 llvm-svn: 228765
* [mips][microMIPS] Implement CodeGen support for SW16 and LW16 instructionsZoran Jovanovic2015-02-042-1/+28
| | | | | | Differential Revision: http://reviews.llvm.org/D6581 llvm-svn: 228149
* [mips] Remove unused check prefix from tests. NFC.Daniel Sanders2015-02-042-18/+18
| | | | | | | | | | | | Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7376 llvm-svn: 228145
* Move the Mips target to storing the ABI in the TargetMachine ratherEric Christopher2015-01-2628-152/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. llvm-svn: 227102
* [mips] Enable arithmetic and binary operations for the i128 data type.Vasileios Kalintiris2015-01-2613-16/+384
| | | | | | | | | | | | | | | | | | Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
* [mips] Add tests for bitwise binary and integer arithmetic operators.Vasileios Kalintiris2015-01-2612-0/+1241
| | | | | | | | | | Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
* Revert "[mips] Fix assertion on i128 addition/subtraction on MIPS64"Vasileios Kalintiris2015-01-262-189/+0
| | | | | | | | This reverts commit r227003. Support for addition/subtraction and various other operations for the i128 data type will be added in a future commit based on the review D7143. llvm-svn: 227082
* [mips] Fix assertion on i128 addition/subtraction on MIPS64Daniel Sanders2015-01-242-0/+189
| | | | | | | | | | | | | | | | Summary: In addition to the included tests, this fixes test/CodeGen/Generic/i128-addsub.ll on a mips64 host. Reviewers: atanasyan, sagar, vmedic Reviewed By: vmedic Subscribers: sdkie, llvm-commits Differential Revision: http://reviews.llvm.org/D6610 llvm-svn: 227003
* [mips] Add registers and ALL check prefix to octeon test case.Kai Nacke2015-01-201-46/+36
| | | | | | | | No functional change. Reviewed by D. Sanders llvm-svn: 226574
* [mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132Kai Nacke2015-01-201-0/+72
| | | | | | | | | This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132. It also includes patterns for instruction selection and test cases. Reviewed by D. Sanders llvm-svn: 226573
* [mips] Fix a typo in the compare patterns for MIPS32r6/MIPS64r6.Daniel Sanders2015-01-151-0/+90
| | | | | | | | | | | | | | Summary: The patterns intended for the SETLE node were actually matching the SETLT node. Reviewers: atanasyan, sstankovic, vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6997 llvm-svn: 226171
* [mips] Refine octeon instructions seq/seqi/sne/sneiKai Nacke2015-01-141-0/+66
| | | | | | | | | | | | | | This commit refines the pattern for the octeon seq/seqi/sne/snei instructions. The target register is set to 0 or 1 according to the result of the comparison. In C, this is something like rd = (unsigned long)(rs == rt) This commit adds a zext to bring the result to i64. With this change the instruction is selected for this type of code. (gcc produces the same code for the above C code.) llvm-svn: 225968
* Revert "Insert random noops to increase security against ROP attacks (llvm)"JF Bastien2015-01-141-26/+0
| | | | | | | This reverts commit: http://reviews.llvm.org/D3392 llvm-svn: 225948
* Insert random noops to increase security against ROP attacks (llvm)JF Bastien2015-01-141-0/+26
| | | | | | | | | | | | | | | | | | | | A pass that adds random noops to X86 binaries to introduce diversity with the goal of increasing security against most return-oriented programming attacks. Command line options: -noop-insertion // Enable noop insertion. -noop-insertion-percentage=X // X% of assembly instructions will have a noop prepended (default: 50%, requires -noop-insertion) -max-noops-per-instruction=X // Randomly generate X noops per instruction. ie. roll the dice X times with probability set above (default: 1). This doesn't guarantee X noop instructions. In addition, the following 'quick switch' in clang enables basic diversity using default settings (currently: noop insertion and schedule randomization; it is intended to be extended in the future). -fdiversify This is the llvm part of the patch. clang part: D3393 http://reviews.llvm.org/D3392 Patch by Stephen Crane (@rinon) llvm-svn: 225908
* [mips][microMIPS] Fix issue with 16b instructions in jr instruction delay slotJozef Kolek2015-01-131-0/+48
| | | | | | | | | 16 bit instructions are not allowed in jr delay slot. Same stands for PseudoIndirectBranch and PseudoReturn. Differential Revision: http://reviews.llvm.org/D6815 llvm-svn: 225798
* [mips] Add support for accessing $gp as a named register.Daniel Sanders2015-01-093-0/+52
| | | | | | | | | | | | | | | | | | | | | Summary: Mips Linux uses $gp to hold a pointer to thread info structure and accesses it with a named register. This makes this work for LLVM. The N32 ABI doesn't quite work yet since the frontend generates incorrect IR for this case. It neglects to truncate the 64-bit GPR to a 32-bit value before converting to a pointer. Given correct IR (as in the testcase in this patch), it works correctly. Reviewers: sstankovic, vmedic, atanasyan Reviewed By: atanasyan Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6893 llvm-svn: 225529
* [mips][microMIPS] Fix bugs related to atomic SC/LL instructionsJozef Kolek2014-12-182-20/+62
| | | | | | | | | Fix bugs related to atomic microMIPS SC/LL instructions: While expanding atomic operations the mips32r2 encoding was emitted instead of microMIPS. Differential Revision: http://reviews.llvm.org/D6659 llvm-svn: 224524
* [mips] Clean up the CodeGen/Mips/inlineasmmemop.ll test. NFC.Toma Tabacu2014-12-181-21/+4
| | | | | | | | | | | | | | | | | | Summary: Improve comments and remove a redundant attribute list. There are no functional changes (to the CHECK's or to the code). Part of these changes were suggested in http://reviews.llvm.org/D6637. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6705 llvm-svn: 224517
* [mips] Set GCC-compatible MIPS asssembler options before inline asm blocks.Toma Tabacu2014-12-174-27/+32
| | | | | | | | | | | | | | | | | | | | Summary: When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives, while GCC uses the default options if an assembly-level function contains inline assembly code. This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example). This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6637 llvm-svn: 224425
* [mips] Fix arguments-struct.ll for Windows and OSX hosts.Daniel Sanders2014-12-161-8/+8
| | | | llvm-svn: 224333
* IR: Make metadata typeless in assemblyDuncan P. N. Exon Smith2014-12-1514-52/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that `Metadata` is typeless, reflect that in the assembly. These are the matching assembly changes for the metadata/value split in r223802. - Only use the `metadata` type when referencing metadata from a call intrinsic -- i.e., only when it's used as a `Value`. - Stop pretending that `ValueAsMetadata` is wrapped in an `MDNode` when referencing it from call intrinsics. So, assembly like this: define @foo(i32 %v) { call void @llvm.foo(metadata !{i32 %v}, metadata !0) call void @llvm.foo(metadata !{i32 7}, metadata !0) call void @llvm.foo(metadata !1, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{metadata !3}, metadata !0) ret void, !bar !2 } !0 = metadata !{metadata !2} !1 = metadata !{i32* @global} !2 = metadata !{metadata !3} !3 = metadata !{} turns into this: define @foo(i32 %v) { call void @llvm.foo(metadata i32 %v, metadata !0) call void @llvm.foo(metadata i32 7, metadata !0) call void @llvm.foo(metadata i32* @global, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{!3}, metadata !0) ret void, !bar !2 } !0 = !{!2} !1 = !{i32* @global} !2 = !{!3} !3 = !{} I wrote an upgrade script that handled almost all of the tests in llvm and many of the tests in cfe (even handling many `CHECK` lines). I've attached it (or will attach it in a moment if you're speedy) to PR21532 to help everyone update their out-of-tree testcases. This is part of PR21532. llvm-svn: 224257
* [mips] Enable code generation for MIPS-III.Vasileios Kalintiris2014-12-121-93/+146
| | | | | | | | | | | | | | | | | | Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 llvm-svn: 224128
* [mips] Support SELECT nodes for targets that don't have conditional-move ↵Vasileios Kalintiris2014-12-121-0/+649
| | | | | | | | | | | | | | | | | | | | | | | | instructions. Summary: For Mips targets that do not have conditional-move instructions, ie. targets before MIPS32 and MIPS-IV, we have to insert a diamond control-flow pattern in order to support SELECT nodes. In order to do that, we add pseudo-instructions with a custom inserter that emits the necessary control-flow that selects the correct value. With this patch we add complete support for code generation of Mips-II targets based on the LLVM test-suite. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6212 llvm-svn: 224124
* [mips][microMIPS] Implement CodeGen support for LI16 instruction.Jozef Kolek2014-12-112-1/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D5840 llvm-svn: 224017
* [mips] Fix passing of small structures for big-endian O32.Daniel Sanders2014-12-021-0/+41
| | | | | | | | | | | | | | | | | | | Summary: Like N32/N64, they must be passed in the upper bits of the register. The new code could be merged with the existing if-statements but I've refrained from doing this since it will make porting the O32 implementation to tablegen harder later. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6463 llvm-svn: 223148
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