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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2015-02-04 15:43:17 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2015-02-04 15:43:17 +0000 |
| commit | 5a1a780c2aa04bac5e5bb7220f74cb66fab70c15 (patch) | |
| tree | dcc6465ddeb61117ae8d39ba87c25a88a465b917 /llvm/test/CodeGen/Mips | |
| parent | fac2371be324d6a3aa0c9622f5147abbc707894e (diff) | |
| download | bcm5719-llvm-5a1a780c2aa04bac5e5bb7220f74cb66fab70c15.tar.gz bcm5719-llvm-5a1a780c2aa04bac5e5bb7220f74cb66fab70c15.zip | |
[mips][microMIPS] Implement CodeGen support for SW16 and LW16 instructions
Differential Revision: http://reviews.llvm.org/D6581
llvm-svn: 228149
Diffstat (limited to 'llvm/test/CodeGen/Mips')
| -rw-r--r-- | llvm/test/CodeGen/Mips/longbranch.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll | 27 |
2 files changed, 28 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Mips/longbranch.ll b/llvm/test/CodeGen/Mips/longbranch.ll index ad0235eb0af..821ced8e7b8 100644 --- a/llvm/test/CodeGen/Mips/longbranch.ll +++ b/llvm/test/CodeGen/Mips/longbranch.ll @@ -124,7 +124,7 @@ end: ; MICROMIPS: $[[BB0]]: ; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) ; MICROMIPS: li16 $[[R2:[0-9]+]], 1 -; MICROMIPS: sw $[[R2]], 0($[[R1]]) +; MICROMIPS: sw16 $[[R2]], 0($[[R1]]) ; MICROMIPS: $[[BB2]]: ; MICROMIPS: jr $ra ; MICROMIPS: nop diff --git a/llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll b/llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll new file mode 100644 index 00000000000..bc095546ceb --- /dev/null +++ b/llvm/test/CodeGen/Mips/micromips-sw-lw-16.ll @@ -0,0 +1,27 @@ +; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm \ +; RUN: -relocation-model=pic -O3 -o - | FileCheck %s + +; Function Attrs: noinline nounwind +define void @bar(i32* %p) #0 { +entry: + %p.addr = alloca i32*, align 4 + store i32* %p, i32** %p.addr, align 4 + %0 = load i32** %p.addr, align 4 + %1 = load i32* %0, align 4 + %add = add nsw i32 7, %1 + %2 = load i32** %p.addr, align 4 + store i32 %add, i32* %2, align 4 + %3 = load i32** %p.addr, align 4 + %add.ptr = getelementptr inbounds i32* %3, i32 1 + %4 = load i32* %add.ptr, align 4 + %add1 = add nsw i32 7, %4 + %5 = load i32** %p.addr, align 4 + %add.ptr2 = getelementptr inbounds i32* %5, i32 1 + store i32 %add1, i32* %add.ptr2, align 4 + ret void +} + +; CHECK: lw16 ${{[0-9]+}}, 0($4) +; CHECK: sw16 ${{[0-9]+}}, 0($4) +; CHECK: lw16 ${{[0-9]+}}, 4(${{[0-9]+}}) +; CHECK: sw16 ${{[0-9]+}}, 4(${{[0-9]+}}) |
