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* [mips] Fix 'l' constraint handling for types smaller than 32 bitsSimon Atanasyan2018-02-122-0/+23
| | | | | | | | | | In case of correct using of the 'l' constraint llvm now generates valid code; otherwise it shows an error message. Initially these triggers an assertion. This commit is the same as r324869 with fixed the test's file name. llvm-svn: 324885
* [mips] Revert rL324869Simon Atanasyan2018-02-122-23/+0
| | | | | | | This commit adds inlineasm-cnstrnt-bad-l.ll which is clashing with inlineasm-cnstrnt-bad-L.ll on case insensitive file systems. llvm-svn: 324882
* [mips] Fix 'l' constraint handling for types smaller than 32 bitsSimon Atanasyan2018-02-122-0/+23
| | | | | | | | In case of correct using of the 'l' constraint llvm now generates valid code; otherwise it shows an error message. Initially these triggers an assertion. llvm-svn: 324869
* [DebugInfo] Don't insert DEBUG_VALUE after terminatorsStefan Maksimovic2018-02-092-2/+2
| | | | | | | | | | | | | | r314974 introduced insertion of DEBUG_VALUEs after each redefinition of debug value register in the slot index range. In case the instruction redefining the debug value register was a terminator, machine verifier would complain since it enforces the rule of no non-terminator instructions following the first terminator. Differential Revision: https://reviews.llvm.org/D42801 llvm-svn: 324734
* [SelectionDAG] Provide adequate register class for RegisterSDNodeStefan Maksimovic2018-02-091-10/+10
| | | | | | | | | | When adding operands to machine instructions in case of RegisterSDNodes, generate a COPY node in case the register class does not match the one in the instruction definition. Differental Revision: https://reviews.llvm.org/D35561 llvm-svn: 324733
* [mips] UnXFAIL gprestore.ll test.Simon Dardis2018-02-091-14/+207
| | | | | | | Repurpose this previously XFAIL'd test to check that jalr uses $25 as per ABI requirements for PIC code. llvm-svn: 324729
* Revert accidental changes that snuck in r324584Stefan Maksimovic2018-02-081-17/+0
| | | | llvm-svn: 324585
* [mips] Define certain instructions in microMIPS32r3Stefan Maksimovic2018-02-084-0/+139
| | | | | | | | | | | | | | | | | | | | Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
* [mips] Support 'y' operand code to print exact log2 of the operandSimon Atanasyan2018-02-072-0/+22
| | | | llvm-svn: 324477
* [mips] Handle 'M' and 'L' operand codes for memory operandsSimon Atanasyan2018-02-071-1/+21
| | | | | | | | Both operand codes now work the same way in case of register or memory operands. It print high-order or low-order word in a double-word register or memory location. llvm-svn: 324476
* [Mips][AMDGPU] Update test cases to not use vector lt/gt compares that can ↵Craig Topper2018-02-071-8/+8
| | | | | | | | | | be simplified to an equality/inequality or to always true/false. For example 'ugt X, 0' can be simplified to 'ne X, 0'. Or 'uge X, 0' is always true. We already simplify this for scalars in SimplifySetCC, but we don't currently for vectors in SimplifySetCC. D42948 proposes to change that. llvm-svn: 324436
* [MIPS] Regenerate vector tests with update scriptSimon Pilgrim2018-02-031-1316/+6782
| | | | | | Hopefully help make this a lot more maintainable llvm-svn: 324180
* [MachineCopyPropagation] Extend pass to do COPY source forwardingGeoff Berry2018-02-014-11/+11
| | | | | | | | | | | | | | | | | | | | | | Summary: This change extends MachineCopyPropagation to do COPY source forwarding and adds an additional run of the pass to the default pass pipeline just after register allocation. This version of this patch uses the newly added MachineOperand::isRenamable bit to avoid forwarding registers is such a way as to violate constraints that aren't captured in the Machine IR (e.g. ABI or ISA constraints). This change is a continuation of the work started in D30751. Reviewers: qcolombet, javed.absar, MatzeB, jonpa, tstellar Subscribers: tpr, mgorny, mcrosier, nhaehnle, nemanjai, jyknight, hfinkel, arsenm, inouehrs, eraman, sdardis, guyblank, fedor.sergeev, aheejin, dschuff, jfb, myatsina, llvm-commits Differential Revision: https://reviews.llvm.org/D41835 llvm-svn: 323991
* [mips] Include EVA instructions in Std2MicroMips mapping tablesAleksandar Beserminji2018-02-011-0/+213
| | | | | | | | | This patch includes EVA instructions in the Std2MicroMips mapping tables, which is required for direct object emission. Differential Revision: https://reviews.llvm.org/D41771 llvm-svn: 323958
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-3133-408/+408
| | | | | | | | | | | | Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
* [mips] Fix incorrect sign extension for fpowi libcallSimon Dardis2018-01-301-0/+65
| | | | | | | | | | | | | | | | | PR36061 showed that during the expansion of ISD::FPOWI, that there was an incorrect zero extension of the integer argument which for MIPS64 would then give incorrect results. Address this with the existing mechanism for correcting sign extensions. This resolves PR36061. Thanks to James Cowgill for reporting the issue! Reviewers: atanasyan, hfinkel Differential Revision: https://reviews.llvm.org/D42537 llvm-svn: 323781
* [AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regsGeoff Berry2018-01-291-1/+1
| | | | | | | | | Summary: Fix a few places that were modifying code after register allocation to set the renamable bit correctly to avoid failing the validation added in D42449. llvm-svn: 323675
* [MIPS] Don't crash on unsized extern types with -mgpoptAlexander Richardson2018-01-261-0/+22
| | | | | | | | | | | | | | Summary: This fixes an assertion when building the FreeBSD MIPS64 kernel. Reviewers: atanasyan, sdardis, emaste Reviewed By: sdardis Subscribers: krytarowski, llvm-commits Differential Revision: https://reviews.llvm.org/D42571 llvm-svn: 323536
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-01-241-1/+1
| | | | | | "the the" -> "the" llvm-svn: 323302
* [mips] Properly select abs and sqrt instructionsStefan Maksimovic2018-01-232-0/+57
| | | | | | | | | | | | | - Alter abs for micromips to have both AFGR64 and FGR64 variants, same as sqrt - Remove sqrt and abs from MicroMips32r6InstrInfo.td, use micromips FGR64 variants - Restrict non-micromips abs/sqrt with NotInMicroMips predicate Differential revision: https://reviews.llvm.org/D41439 llvm-svn: 323184
* [mips] add warnings for using dsp and msa flags with inappropriate revisionsPetar Jovanovic2018-01-221-0/+44
| | | | | | | | | | | Dsp and dspr2 require MIPS revision 2, while msa requires revision 5. Adding warnings for cases when these flags are used with earlier revision. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D40490 llvm-svn: 323131
* Remove alignment argument from memcpy/memmove/memset in favour of alignment ↵Daniel Neilson2018-01-1912-39/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | attributes (Step 1) Summary: This is a resurrection of work first proposed and discussed in Aug 2015: http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html and initially landed (but then backed out) in Nov 2015: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html The @llvm.memcpy/memmove/memset intrinsics currently have an explicit argument which is required to be a constant integer. It represents the alignment of the dest (and source), and so must be the minimum of the actual alignment of the two. This change is the first in a series that allows source and dest to each have their own alignments by using the alignment attribute on their arguments. In this change we: 1) Remove the alignment argument. 2) Add alignment attributes to the source & dest arguments. We, temporarily, require that the alignments for source & dest be equal. For example, code which used to read: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* %src, i32 100, i32 4, i1 false) will now read call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %dest, i8* align 4 %src, i32 100, i1 false) Downstream users may have to update their lit tests that check for @llvm.memcpy/memmove/memset call/declaration patterns. The following extended sed script may help with updating the majority of your tests, but it does not catch all possible patterns so some manual checking and updating will be required. s~declare void @llvm\.mem(set|cpy|move)\.p([^(]*)\((.*), i32, i1\)~declare void @llvm.mem\1.p\2(\3, i1)~g s~call void @llvm\.memset\.p([^(]*)i8\(i8([^*]*)\* (.*), i8 (.*), i8 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i8(i8\2* \3, i8 \4, i8 \5, i1 \6)~g s~call void @llvm\.memset\.p([^(]*)i16\(i8([^*]*)\* (.*), i8 (.*), i16 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i16(i8\2* \3, i8 \4, i16 \5, i1 \6)~g s~call void @llvm\.memset\.p([^(]*)i32\(i8([^*]*)\* (.*), i8 (.*), i32 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i32(i8\2* \3, i8 \4, i32 \5, i1 \6)~g s~call void @llvm\.memset\.p([^(]*)i64\(i8([^*]*)\* (.*), i8 (.*), i64 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i64(i8\2* \3, i8 \4, i64 \5, i1 \6)~g s~call void @llvm\.memset\.p([^(]*)i128\(i8([^*]*)\* (.*), i8 (.*), i128 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.memset.p\1i128(i8\2* \3, i8 \4, i128 \5, i1 \6)~g s~call void @llvm\.memset\.p([^(]*)i8\(i8([^*]*)\* (.*), i8 (.*), i8 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i8(i8\2* align \6 \3, i8 \4, i8 \5, i1 \7)~g s~call void @llvm\.memset\.p([^(]*)i16\(i8([^*]*)\* (.*), i8 (.*), i16 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i16(i8\2* align \6 \3, i8 \4, i16 \5, i1 \7)~g s~call void @llvm\.memset\.p([^(]*)i32\(i8([^*]*)\* (.*), i8 (.*), i32 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i32(i8\2* align \6 \3, i8 \4, i32 \5, i1 \7)~g s~call void @llvm\.memset\.p([^(]*)i64\(i8([^*]*)\* (.*), i8 (.*), i64 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i64(i8\2* align \6 \3, i8 \4, i64 \5, i1 \7)~g s~call void @llvm\.memset\.p([^(]*)i128\(i8([^*]*)\* (.*), i8 (.*), i128 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.memset.p\1i128(i8\2* align \6 \3, i8 \4, i128 \5, i1 \7)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i8\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i8 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i8(i8\3* \4, i8\5* \6, i8 \7, i1 \8)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i16\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i16 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i16(i8\3* \4, i8\5* \6, i16 \7, i1 \8)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i32\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i32 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i32(i8\3* \4, i8\5* \6, i32 \7, i1 \8)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i64\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i64 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i64(i8\3* \4, i8\5* \6, i64 \7, i1 \8)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i128\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i128 (.*), i32 [01], i1 ([^)]*)\)~call void @llvm.mem\1.p\2i128(i8\3* \4, i8\5* \6, i128 \7, i1 \8)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i8\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i8 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i8(i8\3* align \8 \4, i8\5* align \8 \6, i8 \7, i1 \9)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i16\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i16 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i16(i8\3* align \8 \4, i8\5* align \8 \6, i16 \7, i1 \9)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i32\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i32 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i32(i8\3* align \8 \4, i8\5* align \8 \6, i32 \7, i1 \9)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i64\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i64 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i64(i8\3* align \8 \4, i8\5* align \8 \6, i64 \7, i1 \9)~g s~call void @llvm\.mem(cpy|move)\.p([^(]*)i128\(i8([^*]*)\* (.*), i8([^*]*)\* (.*), i128 (.*), i32 ([0-9]*), i1 ([^)]*)\)~call void @llvm.mem\1.p\2i128(i8\3* align \8 \4, i8\5* align \8 \6, i128 \7, i1 \9)~g The remaining changes in the series will: Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing source and dest alignments. Step 3) Update Clang to use the new IRBuilder API. Step 4) Update Polly to use the new IRBuilder API. Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API, and those that use use MemIntrinsicInst::[get|set]Alignment() to use getDestAlignment() and getSourceAlignment() instead. Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the MemIntrinsicInst::[get|set]Alignment() methods. Reviewers: pete, hfinkel, lhames, reames, bollu Reviewed By: reames Subscribers: niosHD, reames, jholewinski, qcolombet, jfb, sanjoy, arsenm, dschuff, dylanmckay, mehdi_amini, sdardis, nemanjai, david2050, nhaehnle, javed.absar, sbc100, jgravelle-google, eraman, aheejin, kbarton, JDevlieghere, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, llvm-commits Differential Revision: https://reviews.llvm.org/D41675 llvm-svn: 322965
* [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.Puyan Lotfi2018-01-101-9/+9
| | | | | | | | | | Planning to add support for named vregs. This puts is in a conundrum since physregs are named as well. To rectify this we need to use a sigil other than '%' for physregs in MIR. We've settled on using '$' for physregs but first we must repurpose it from external symbols using it, which is what this commit is all about. We think '&' will have familiar semantics for C/C++ users. llvm-svn: 322146
* [mips] Replace assert by an error messageSimon Atanasyan2017-12-292-0/+35
| | | | | | | | Initially, if the `c` constraint applied to the wrong data type that causes LLVM to assert. This commit replaces the assert by an error message. llvm-svn: 321565
* [SelectionDAG] Reverse the order of operands in the ISD::ADD created by ↵Craig Topper2017-12-221-1/+1
| | | | | | | | | | TargetLowering::getVectorElementPointer so that the FrameIndex is on the left. This seems to improve X86's ability to match this into an address computation. Otherwise the other operand gets assigned to the base register and the stack pointer + frame index ends up in the index register. But index registers can't encode ESP/RSP so we end up having to move it into another register to meet the constraint. I could try to improve the address matcher in X86, but swapping the producer seemed easier. Several other places already have the operands in this order so this is at least consistent. llvm-svn: 321370
* [mips] Add test case to check that calls to mcount follow long calls / short ↵Simon Atanasyan2017-12-221-0/+19
| | | | | | calls options. NFC llvm-svn: 321357
* [mips] Handle the emission of microMIPSr6 sll instruction when used as a nop.Simon Dardis2017-12-191-0/+46
| | | | | | | This instruction is encoded as zero, so we have handle that case when checking for unimplemented opcodes when producing the encoding for an instruction. llvm-svn: 321066
* Reland "[mips] Fix the target specific instruction verifier"Simon Dardis2017-12-1826-35/+89
| | | | | | | | | | | | | Fix an off by one error in the bounds checking for 'dinsu' and update the ranges in the test comments so that they are accurate. This version has the correct commit message. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41183 llvm-svn: 320991
* Revert "[mips] Fix the target specific instruction verifier"Simon Dardis2017-12-1826-89/+35
| | | | | | This reverts commit r320974. The commit message lacked the Differential Revison: line. llvm-svn: 320975
* [mips] Fix the target specific instruction verifierSimon Dardis2017-12-1826-35/+89
| | | | | | | | | | | Fix an off by one error in the bounds checking for 'dinsu' and update the ranges in the test comments so that they are accurate. Reviewers: atanasyan https://reviews.llvm.org/D41183 llvm-svn: 320974
* [mips] Update some tests before posting a patch, NFC.Simon Dardis2017-12-146-1471/+6350
| | | | llvm-svn: 320715
* [mips] Add partial support for R6 in the long branch passSimon Dardis2017-12-141-155/+309
| | | | | | | | | | | | | | | | | | | | MIPSR6 introduced several new jump instructions and deprecated the use of the 'j' instruction. For microMIPS32R6, 'j' was removed entirely and it only has non delay slot jumps. This patch adds support for MIPSR6 by using some R6 instructions-- 'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'-- and modifies the sequences not to use delay slots for R6. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: dschuff, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D40786 llvm-svn: 320703
* [mips] Provide additional DSP bitconvert patternsStefan Maksimovic2017-12-131-0/+47
| | | | | | | | | Previously, v2i16 -> f32 bitcast could not be matched. Add patterns to support matching this and similar types of bitcasts. Differential revision: https://reviews.llvm.org/D40959 llvm-svn: 320562
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-1121-342/+5
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-043-5/+5
| | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
* [CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih2017-11-302-2/+2
| | | | | | | | | | | | | | output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-2/+2
| | | | | | | | | | | As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
* [DAGCombine] Disable finding better chains for stores at O0Simon Dardis2017-11-281-0/+613
| | | | | | | | | | | | | | | | | | | | | | | | | | | Unoptimized IR can have linear sequences of stores to an array, where the initial GEP for the first store is formed from the pointer to the array, and the GEP for each store after the first is formed from the previous GEP with some offset in an inductive fashion. The (large) resulting DAG when analyzed by DAGCombine undergoes an excessive number of combines as each store node is examined every time its' offset node is combined with any child of the offset. One of the transformations is findBetterNeighborChains which assists MergeConsecutiveStores. The former relies on repeated chain walking to do its' work, however MergeConsecutiveStores is disabled at O0 which makes the transformation redundant. Any optimization level other than O0 would invoke InstCombine which would resolve the chain of GEPs into flat base + offset GEP for each store which does not exhibit the repeated examination of each store to the array. Disabling this optimization fixes an excessive compile time issue (30~ minutes for the test case provided) at O0. Reviewers: niravd, craig.topper, t.p.northover Differential Revision: https://reviews.llvm.org/D40193 llvm-svn: 319142
* [DAG] Do MergeConsecutiveStores again before Instruction SelectionNirav Dave2017-11-272-16/+17
| | | | | | | | | | | | | | | | Summary: Now that store-merge is only generates type-safe stores, do a second pass just before instruction selection to allow lowered intrinsics to be merged as well. Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33675 llvm-svn: 319036
* [mips] fix asmstring of Ext and Ins instructions and mips16 JALRC/JRCPetar Jovanovic2017-11-271-0/+62
| | | | | | | | | | | | | | | Make the print format consistent with other assembler instructions. Adding a tab character instead of space in asmstring of Ext and Ins instructions. Removing space around the tab character for JALRC and replacing space with tab in JRC. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38144 llvm-svn: 319030
* [mips] Set microMIPS ASE flagAleksandar Beserminji2017-11-241-0/+11
| | | | | | | | | | This patch fixes an issue where microMIPS ASE flag is not set when a function has micromips attribute or when .set micromips directive is used. Differential Revision: https://reviews.llvm.org/D40316 llvm-svn: 318948
* [mips] Use the delay slot filler to convert branches for microMIPSR6.Simon Dardis2017-11-233-6/+5
| | | | | | | | | | | | | | | | | | The MIPS delay slot filler converts delay slot branches into compact forms for the MIPS ISAs which support them. For branches that compare (in)equality with with zero, it converts them into branches with implict zero register operands. These branches have a slightly greater range than normal two register operands branches. Changing the branches at this point in the pipeline offers the long branch pass the ability to mark better judgements if a long branch sequence is required. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D40314 llvm-svn: 318908
* [mips] Reorder target specific passesSimon Dardis2017-11-201-0/+154
| | | | | | | | | Move the hazard scheduling pass to after the long branch pass, as the long branch pass can create forbiddden slot hazards. Rather than complicating the implementation of the long branch pass to handle forbidden slot hazards, just reorder the passes. llvm-svn: 318657
* [mips] Improve genConstMult() to work with arbitrary precisionPetar Jovanovic2017-11-151-0/+45
| | | | | | | | | | | APInt is now used instead of uint64_t in function genConstMult() allowing multiplication optimizations with constants of arbitrary length. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38130 llvm-svn: 318296
* [mips] Simplify test for 5.0.1 (NFC)Simon Dardis2017-11-141-18/+9
| | | | | | | Simplify testing that an emergency spill slot is used when MSA is used so that it can be included in the 5.0.1 release. llvm-svn: 318172
* [mips] Correct microMIP's jump and add unconditional branch pseudoSimon Dardis2017-11-091-9/+17
| | | | | | | | | | | | | | Correct the definition of 'j' as being unavailable for microMIPS32R6 and provide the 'b' assembly idiom for codegen purposes for microMIPS32r3. Provide the necessary 'br' pattern for microMIPS32R6 as it now longer incorrectly uses the 'j' instruction. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39741 llvm-svn: 317801
* [mips] Guard indirect and tailcall pseudo instructions correctly.Simon Dardis2017-11-082-1/+74
| | | | | | | | | | | Previously these pseudo instructions were not guarded by ISA, so their select was dependant on the ordering of the entries in the DAG matcher. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39723 llvm-svn: 317681
* [mips] Match 'ins' and its' variants with C++ codeSimon Dardis2017-11-031-5/+9
| | | | | | | | | | | | | Change the ISel matching of 'ins', 'dins[mu]' from tablegen code to C++ code. This resolves an issue where ISel would select 'dins' instead of 'dinsm' when the instructions size and position were individually in range but their sum was out of range according to the ISA specification. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39117 llvm-svn: 317331
* [mips] Use register scavenging with MSA.Simon Dardis2017-11-022-17/+253
| | | | | | | | | | | | | | | | | MSA stores and loads to the stack are more likely to require an emergency GPR spill slot due to the smaller offsets available with those instructions. Handle this by overestimating the size of the stack by determining the largest offset presuming that all callee save registers are spilled and accounting of incoming arguments when determining whether an emergency spill slot is required. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39056 llvm-svn: 317204
* [mips] Fix PR35071Simon Dardis2017-10-261-0/+73
| | | | | | | | | | | | | | | | | | | | PR35071 exposed the fact that MipsInstrInfo::removeBranch did not walk past debug instructions when removing branches for the control flow optimizer, which lead to duplicated conditional branches. If the target of the branch was a removable block, only the conditional branch in the terminating position would have it's MBB operands updated, leaving the first branch with a dangling MBB operand. The MIPS long branch pass would then trigger an assertion when attempting to examine the instruction with dangling MBB operand. This resolves PR35071. Thanks to Alex Richardson for reporting the issue! Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39288 llvm-svn: 316654
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