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| author | Nirav Dave <niravd@google.com> | 2017-11-27 15:28:15 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2017-11-27 15:28:15 +0000 |
| commit | db77e57ea86d941a4262ef60261692f4cb6893e6 (patch) | |
| tree | 5ea93e1652b4f3065657d9618c69315582b377a4 /llvm/test/CodeGen/Mips | |
| parent | 948a915924ded9364ddf2d55ad69f47b37bc0843 (diff) | |
| download | bcm5719-llvm-db77e57ea86d941a4262ef60261692f4cb6893e6.tar.gz bcm5719-llvm-db77e57ea86d941a4262ef60261692f4cb6893e6.zip | |
[DAG] Do MergeConsecutiveStores again before Instruction Selection
Summary:
Now that store-merge is only generates type-safe stores, do a second
pass just before instruction selection to allow lowered intrinsics to
be merged as well.
Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33675
llvm-svn: 319036
Diffstat (limited to 'llvm/test/CodeGen/Mips')
| -rw-r--r-- | llvm/test/CodeGen/Mips/cconv/vector.ll | 30 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll | 3 |
2 files changed, 17 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/Mips/cconv/vector.ll b/llvm/test/CodeGen/Mips/cconv/vector.ll index 5a88d064fe7..02d6272bb7e 100644 --- a/llvm/test/CodeGen/Mips/cconv/vector.ll +++ b/llvm/test/CodeGen/Mips/cconv/vector.ll @@ -821,8 +821,10 @@ entry: ; MIPS32R5: jal ; MIPS32R5: sw $2, {{[0-9]+}}($sp) -; MIPS32R5-DAG: sb ${{[0-9]+}}, 1(${{[0-9]+}}) -; MIPS32R5-DAG; sb ${{[0-9]+}}, %lo(gv2i8)(${{[0-9]+}}) +; MIPS32R5-DAG; sh ${{[0-9]+}}, %lo(gv2i8)(${{[0-9]+}}) + +; MIPS32R5-NOT: sb ${{[0-9]+}}, 1(${{[0-9]+}}) +; MIPS32R5-NOT; sb ${{[0-9]+}}, %lo(gv2i8)(${{[0-9]+}}) ; MIPS64EB: daddiu $4, $zero, 1543 ; MIPS64EB: daddiu $5, $zero, 3080 @@ -870,14 +872,14 @@ entry: ; MIPS32-NOT: ori $6 ; MIPS32-NOT: ori $7 -; MIPS32R5-DAG: lw $4, {{[0-9]+}}($sp) -; MIPS32R5-DAG: lw $5, {{[0-9]+}}($sp) +; MIPS32R5-NOT: lw $4, {{[0-9]+}}($sp) +; MIPS32R5-NOT: lw $5, {{[0-9]+}}($sp) ; MIPS64: ori $4 ; MIPS64: ori $5 -; MIPS64R5: lw $4 -; MIPS64R5: lw $5 +; MIPS64R5-NOT: lw $4 +; MIPS64R5-NOT: lw $5 ; MIPS32: jal i8_4 ; MIPS64: jalr $25 @@ -996,14 +998,14 @@ entry: ; MIPS32-DAG: ori $4 ; MIPS32-DAG: ori $5 -; MIPS32R5-DAG: lw $4 -; MIPS32R5-DAG: lw $5 +; MIPS32R5-NOT: lw $4 +; MIPS32R5-NOT: lw $5 ; MIPS64: ori $4 ; MIPS64: ori $5 -; MIPS64R5-DAG: lw $4 -; MIPS64R5-DAG: lw $5 +; MIPS64R5-NOT: lw $4 +; MIPS64R5-NOT: lw $5 ; MIPS32: jal i16_2 ; MIPS64: jalr $25 @@ -1037,8 +1039,8 @@ entry: ; MIPS64-DAG: daddiu $4 ; MIPS64-DAG: daddiu $5 -; MIPS64R5-DAG: ld $4 -; MIPS64R5-DAG: ld $5 +; MIPS64R5-NOT: ld $4 +; MIPS64R5-NOT: ld $5 ; MIPS32: jal i16_4 ; MIPS64: jalr $25 @@ -1133,8 +1135,8 @@ entry: ; MIPS64: daddiu $4 ; MIPS64: daddiu $5 -; MIPS64R5-DAG: ld $4 -; MIPS64R5-DAG: ld $5 +; MIPS64R5-NOT ld $4 +; MIPS64R5-NOT: ld $5 ; MIPS32: jal i32_2 ; MIPS64: jalr $25 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll b/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll index 3c7df4a5e99..f7b8ea5f9e1 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll @@ -12,8 +12,7 @@ define i1 @via_stack_bug(i8 signext %idx) { ; ALL-LABEL: via_stack_bug: ; ALL-DAG: addiu [[ONE:\$[0-9]+]], $zero, 1 -; ALL-DAG: sb [[ONE]], 7($sp) -; ALL-DAG: sb $zero, 6($sp) +; ALL-DAG: sh [[ONE]], 6($sp) ; ALL-DAG: andi [[MASKED_IDX:\$[0-9]+]], $4, 1 ; ALL-DAG: addiu [[VPTR:\$[0-9]+]], $sp, 6 ; ALL-DAG: or [[EPTR:\$[0-9]+]], [[MASKED_IDX]], [[VPTR]] |
