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* Expand pseudos/macros for Selt. This is the last of the complexReed Kotler2013-02-232-10/+11
| | | | | | macros.The rest is some small misc. stuff. llvm-svn: 175950
* [mips] Emit call16 operator instead of got_disp. The former allows lazy binding.Akira Hatanaka2013-02-222-14/+29
| | | | llvm-svn: 175920
* Expand mips16 SelT form pseudso/macros.Reed Kotler2013-02-227-4/+85
| | | | llvm-svn: 175862
* Expand the sel pseudo/macro. This generates basic blocks where previouslyReed Kotler2013-02-211-3/+3
| | | | | | | there were inline br .+4 instructions. Soon everything can enjoy the full instruction scheduling experience. llvm-svn: 175718
* Expand pseudos/macros:Reed Kotler2013-02-2013-15/+15
| | | | | | | | SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16 $T8 shows up as register $24 when emitted from C++ code so we had to change some tests that were already there for this functionality. llvm-svn: 175593
* Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,Reed Kotler2013-02-192-0/+184
| | | | | | BtnezT8SltiX16, BtnezT8SltiuX16 . llvm-svn: 175486
* Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.Reed Kotler2013-02-192-0/+198
| | | | llvm-svn: 175474
* Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.Reed Kotler2013-02-181-0/+96
| | | | llvm-svn: 175420
* Expand pseudo/macro BteqzT8SltX16.Reed Kotler2013-02-181-0/+98
| | | | llvm-svn: 175417
* Expand macro/pseudo BteqzT8CmpX16.Reed Kotler2013-02-181-0/+96
| | | | llvm-svn: 175416
* Beginning of expanding all current mips16 macro/pseudo instruction sequences.Reed Kotler2013-02-181-0/+95
| | | | | | | | | | This expansion will be moved to expandISelPseudos as soon as I can figure out how to do that. There are other instructions which use this ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all, I will delete the macro asm string text so it has no way to be used in the future. llvm-svn: 175413
* Fix minor mips16 issues in directives for function prologue. Probably this doesReed Kotler2013-02-151-4/+20
| | | | | | | not matter but makes it more gcc compatible which avoids possible subtle problems. Also, turned back on a disabled check in helloworld.ll. llvm-svn: 175237
* For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler2013-02-131-0/+31
| | | | | | | | | | if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. llvm-svn: 175073
* Make jumptables work for -staticReed Kotler2013-02-131-0/+71
| | | | llvm-svn: 175044
* Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are theReed Kotler2013-02-081-0/+30
| | | | | | | | | | same so we put in the comment field an indicator when we think we are emitting the 16 bit version. For the direct object emitter, the difference is important as well as for other passes which need an accurate count of program size. There will be other similar putbacks to this for various instructions. llvm-svn: 174747
* When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler2013-02-081-0/+61
| | | | | | | | allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. llvm-svn: 174696
* Make sure we call externals from libraries properly when -static.Reed Kotler2013-02-071-0/+13
| | | | | | For example, when we are doing mips16 hard float or soft float. llvm-svn: 174583
* Enable jumps when in -static mode.Reed Kotler2013-02-071-0/+4
| | | | llvm-svn: 174580
* [mips] Do not use function CC_MipsN_VarArg unless the function being analyzedAkira Hatanaka2013-02-051-0/+14
| | | | | | | | | | | is a vararg function. The original code was examining flag OutputArg::IsFixed to determine whether CC_MipsN_VarArg or CC_MipsN should be called. This is not correct, since this flag is often set to false when the function being analyzed is a non-variadic function. llvm-svn: 174442
* This patch that sets the EmitAlias flag in td files Jack Carter2013-02-051-2/+2
| | | | | | | | | | | | | and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
* Start static relocation implementation for mips16.Reed Kotler2013-02-021-0/+7
| | | | | | This checkin makes hello world work. llvm-svn: 174264
* [mips] Test case for r173862.Akira Hatanaka2013-01-302-0/+164
| | | | | | Patch by Sasa Stankovic. llvm-svn: 173863
* [mips] Set flag neverHasSideEffects flag on some of the floating point ↵Akira Hatanaka2013-01-251-0/+13
| | | | | | instructions. llvm-svn: 173401
* The next phase of Mips16 hard float implementation.Reed Kotler2013-01-241-0/+256
| | | | | | | | | | | | | | | | Allow Mips16 routines to call Mips32 routines that have abi requirements that either arguments or return values are passed in floating point registers. This handles only the pic case. We have not done non pic for Mips16 yet in any form. The libm functions are Mips32, so with this addition we have a complete Mips16 hard float implementation. We still are not able to complete mix Mip16 and Mips32 with hard float. That will be the next phase which will have several steps. For Mips32 to freely call Mips16 some stub functions must be created. llvm-svn: 173320
* [mips] Implement MipsRegisterInfo::getRegPressureLimit.Akira Hatanaka2013-01-223-7/+7
| | | | llvm-svn: 173197
* [mips] MipsTargetLowering::getSetCCResultType should return a vector type ifAkira Hatanaka2013-01-041-0/+16
| | | | | | vectors are being compared. llvm-svn: 171517
* Add test case for r170674Reed Kotler2012-12-211-0/+29
| | | | llvm-svn: 170823
* fix most of remaining issues with large frames.Reed Kotler2012-12-201-2/+2
| | | | | | | | | | these patches are tested a lot by test-suite but make check tests are forthcoming once the next few patches that complete this are committed. with the next few patches the pass rate for mips16 is near 100% llvm-svn: 170656
* [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copyAkira Hatanaka2012-12-206-18/+18
| | | | | | | | | | | physical register $r1 to $r0. GNU disassembler recognizes an "or" instruction as a "move", and this change makes the disassembled code easier to read. Original patch by Reed Kotler. llvm-svn: 170655
* This patch is needed to make c++ exceptions work for mips16.Reed Kotler2012-12-161-0/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mips16 is really a processor decoding mode (ala thumb 1) and in the same program, mips16 and mips32 functions can exist and can call each other. If a jal type instruction encounters an address with the lower bit set, then the processor switches to mips16 mode (if it is not already in it). If the lower bit is not set, then it switches to mips32 mode. The linker knows which functions are mips16 and which are mips32. When relocation is performed on code labels, this lower order bit is set if the code label is a mips16 code label. In general this works just fine, however when creating exception handling tables and dwarf, there are cases where you don't want this lower order bit added in. This has been traditionally distinguished in gas assembly source by using a different syntax for the label. lab1: ; this will cause the lower order bit to be added lab2=. ; this will not cause the lower order bit to be added In some cases, it does not matter because in dwarf and debug tables the difference of two labels is used and in that case the lower order bits subtract each other out. To fix this, I have added to mcstreamer the notion of a debuglabel. The default is for label and debug label to be the same. So calling EmitLabel and EmitDebugLabel produce the same result. For various reasons, there is only one set of labels that needs to be modified for the mips exceptions to work. These are the "$eh_func_beginXXX" labels. Mips overrides the debug label suffix from ":" to "=." . This initial patch fixes exceptions. More changes most likely will be needed to DwarfCFException to make all of this work for actual debugging. These changes will be to emit debug labels in some places where a simple label is emitted now. Some historical discussion on this from gcc can be found at: http://gcc.gnu.org/ml/gcc-patches/2008-08/msg00623.html http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01273.html llvm-svn: 170279
* This code implements most of mips16 hardfloat as it is done by gcc.Reed Kotler2012-12-151-0/+381
| | | | | | | | | | | | | | | | In this case, essentially it is soft float with different library routines. The next step will be to make this fully interoperational with mips32 floating point and that requires creating stubs for functions with signatures that contain floating point types. I have a more sophisticated design for mips16 hardfloat which I hope to implement at a later time that directly does floating point without the need for function calls. The mips16 encoding has no floating point instructions so one needs to switch to mips32 mode to execute floating point instructions. llvm-svn: 170259
* [mips] Do not copy GOT address to register $gp if the function being called hasAkira Hatanaka2012-12-131-0/+27
| | | | | | internal linkage. llvm-svn: 170092
* Fix a logic bug in inline expansion of memcpy / memset with an overlappingEvan Cheng2012-12-121-0/+11
| | | | | | | load / store pair. It's not legal to use a wider load than the size of the remaining bytes if it's the first pair of load / store. llvm-svn: 170018
* [mips] Generate big GOT code.Akira Hatanaka2012-11-211-0/+50
| | | | llvm-svn: 168460
* Initial implementation of MipsTargetLowering::isLegalAddressingMode.Akira Hatanaka2012-11-171-0/+41
| | | | llvm-svn: 168230
* [mips] Fix delay slot filler so that instructions with register operand $1 areAkira Hatanaka2012-11-161-0/+32
| | | | | | allowed in branch delay slot. llvm-svn: 168131
* [mips] Custom-lower ISD::FRAME_TO_ARGS_OFFSET node.Akira Hatanaka2012-11-071-0/+63
| | | | | | Patch by Sasa Stankovic. llvm-svn: 167548
* [mips] Set flag neverHasSideEffects flag on floating point conversionAkira Hatanaka2012-11-031-0/+16
| | | | | | instructions. llvm-svn: 167348
* [mips] Set flag isAsCheapAsAMove flag on instruction LUi.Akira Hatanaka2012-11-031-0/+25
| | | | llvm-svn: 167345
* [mips] Stop reserving register AT and use register scavenger when a scratchAkira Hatanaka2012-11-031-4/+18
| | | | | | register is needed. llvm-svn: 167341
* [mips] Fix bug in test case. Disable machine LICM to prevent instruction fromAkira Hatanaka2012-11-021-2/+3
| | | | | | being moved out of a basic block. llvm-svn: 167322
* [mips] Use register number instead of name to print register $AT.Akira Hatanaka2012-11-023-13/+13
| | | | llvm-svn: 167315
* [mips] Delete MipsFunctionInfo::EmitNOAT. Unconditionally print directiveAkira Hatanaka2012-11-021-0/+11
| | | | | | | "set .noat" so that the assembler doesn't issue warnings when register $AT is used. llvm-svn: 167310
* [mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enablesAkira Hatanaka2012-10-311-0/+26
| | | | | | re-materialization of immediate loads. llvm-svn: 167153
* Test case for r167039. Check that tail-call optimization is disabled forAkira Hatanaka2012-10-311-0/+23
| | | | | | mips16. llvm-svn: 167139
* Implement ADJCALLSTACKUP and ADJCALLSTACKDOWNReed Kotler2012-10-311-26/+58
| | | | llvm-svn: 167107
* [mips] Allow tail-call optimization for vararg functions and functions whichAkira Hatanaka2012-10-301-1/+65
| | | | | | use the caller's stack. llvm-svn: 167048
* Change mips16 delay slot jumps to non delay slot forms by default.Reed Kotler2012-10-302-3/+3
| | | | | | | | We will make them delay slot forms if there is something that can be placed in the delay slot during a separate pass. Mips16 extended instructions cannot be placed in delay slots. llvm-svn: 166990
* Implement patterns for extloadi8 and extloadi16Reed Kotler2012-10-291-0/+69
| | | | llvm-svn: 166960
* Expand all atomic ops for mips16.Reed Kotler2012-10-291-0/+40
| | | | llvm-svn: 166935
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