| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE. | Daniel Sanders | 2015-10-15 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407 | ||||
| * | [Mips] Adjust float ABI settings in case of MIPS16 mode. | Simon Atanasyan | 2013-11-19 | 1 | -1/+1 |
| | | | | | | | | | | | | Hard float for mips16 means essentially to compile as soft float but to use a runtime library for soft float that is written with native mips32 floating point instructions (those runtime routines run in mips32 hard float mode). The patch reviewed by Reed Kotler. llvm-svn: 195123 | ||||
| * | Create a pattern for the "trap" instruction. | Reed Kotler | 2013-08-07 | 1 | -0/+13 |
| llvm-svn: 187863 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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