| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes ↵ | Guillaume Chatelet | 2019-09-11 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608 | ||||
| * | [MIPS] Fix a incorrect test. (NFC) | Simon Dardis | 2019-02-23 | 1 | -2/+2 |
| | | | | | | | | This test is incorrect as it should be using the microMIPSR6 instruction to return, not the microMIPS version. llvm-svn: 354726 | ||||
| * | Followup on Proposal to move MIR physical register namespace to '$' sigil. | Puyan Lotfi | 2018-01-31 | 1 | -3/+3 |
| | | | | | | | | | | | | | Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922 | ||||
| * | [AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regs | Geoff Berry | 2018-01-29 | 1 | -1/+1 |
| | | | | | | | | | | Summary: Fix a few places that were modifying code after register allocation to set the renamable bit correctly to avoid failing the validation added in D42449. llvm-svn: 323675 | ||||
| * | [mips] Handle the emission of microMIPSr6 sll instruction when used as a nop. | Simon Dardis | 2017-12-19 | 1 | -0/+46 |
| This instruction is encoded as zero, so we have handle that case when checking for unimplemented opcodes when producing the encoding for an instruction. llvm-svn: 321066 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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