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* [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add ↵Zlatko Buljan2016-05-041-0/+10
| | | | | | | | tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions Differential Revision: http://reviews.llvm.org/D19857 llvm-svn: 268491
* [Mips] Adjust float ABI settings in case of MIPS16 mode.Simon Atanasyan2013-11-191-1/+1
| | | | | | | | | | | Hard float for mips16 means essentially to compile as soft float but to use a runtime library for soft float that is written with native mips32 floating point instructions (those runtime routines run in mips32 hard float mode). The patch reviewed by Reed Kotler. llvm-svn: 195123
* Let rotr and bswap be handled by expansion for Mips16 since we don'tReed Kotler2013-10-081-0/+5
| | | | | | have native instructions for this. llvm-svn: 192207
* Change names for MIPS "generic" processors defined in Mips.td to match what GNUAkira Hatanaka2011-11-291-1/+1
| | | | | | | | | | tools use. Patch by Simon Atanasyan. "mips32r1" => "mips32" "4ke" => mips32r2" "mips64r1" => "mips64" llvm-svn: 145451
* Remove unnecessary checking of register operands.Akira Hatanaka2011-09-301-1/+1
| | | | llvm-svn: 140872
* Add ROTR and ROTRV mips32 instructions. Patch by Akira HatanakaBruno Cardoso Lopes2010-12-091-0/+40
llvm-svn: 121377
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