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* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-111-2/+0
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* evert "[mips] Fix test mips64fpldst.ll with machine verifier enabled"Simon Dardis2017-06-071-6/+6
| | | | | | | This reverts commit r301394. It broke some internal buildbots, reverting while the issue is being investigated. llvm-svn: 304896
* [mips] Fix test mips64fpldst.ll with machine verifier enabledSagar Thakur2017-04-261-6/+6
| | | | | | | | | Removed micro mips register classes for gp initialization because gp initialization uses pure mips64 instruction. Even when compiling for micro mips, gp initialization can be done with pure mips64 instructions. Reviewed by Simon Dardis Differential: D32286 llvm-svn: 301394
* [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and ↵Zlatko Buljan2016-07-111-13/+15
| | | | | | | | SWC2 instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D18824 llvm-svn: 275050
* [mips] Make Static a default relocation model for MIPS codegenPetar Jovanovic2016-04-111-4/+4
| | | | | | | | | | | | This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
* Move the Mips target to storing the ABI in the TargetMachine ratherEric Christopher2015-01-261-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | than on MipsSubtargetInfo. This required a bit of massaging in the MC level to handle this since MC is a) largely a collection of disparate classes with no hierarchy, and b) there's no overarching equivalent to the TargetMachine, instead only the subtarget via MCSubtargetInfo (which is the base class of TargetSubtargetInfo). We're now storing the ABI in both the TargetMachine level and in the MC level because the AsmParser and the TargetStreamer both need to know what ABI we have to parse assembly and emit objects. The target streamer has a pointer to the one in the asm parser and is updated when the asm parser is created. This is fragile as the FIXME comment notes, but shouldn't be a problem in practice since we always create an asm parser before attempting to emit object code via the assembler. The TargetMachine now contains the ABI so that the DataLayout can be constructed dependent upon ABI. All testcases have been updated to use the -target-abi command line flag so that we can set the ABI without using a subtarget feature. Should be no change visible externally here. llvm-svn: 227102
* [mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 ↵Daniel Sanders2014-04-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tests with -mcpu=mips4 as a starting point Summary: Two exceptions to this: test/CodeGen/Mips/octeon.ll test/CodeGen/Mips/octeon_popcnt.ll these test extensions to MIPS64 One test is altered for MIPS-IV: test/CodeGen/Mips/mips64countleading.ll Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests that dclo/dclz are not emitted. Four tests fail and are not in this patch: test/CodeGen/Mips/abicalls.ll test/CodeGen/Mips/fcopysign-f32-f64.ll test/CodeGen/Mips/fcopysign.ll test/CodeGen/Mips/stack-alignment.ll Depends on D3343 Reviewers: matheusalmeida, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3344 llvm-svn: 206185
* [mips] Make it impossible to have UnknownABI in CodeGen and Integrated ↵Daniel Sanders2014-02-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Assembler. Summary: This removes the need to coerce UnknownABI to the default ABI (O32 for MIPS32, N64 for MIPS64 [*]) in both MipsSubtarget and MipsAsmParser. Clang has been updated to disable both possible default ABI's before enabling the ABI it intends to use. [*] N64 being the default for MIPS64 is not actually correct. However N32 is not fully implemented/tested yet. Depends on: D2830 Reviewers: jacksprat, matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D2832 Differential Revision: http://llvm-reviews.chandlerc.com/D2846 llvm-svn: 201792
* Reapply 154038 without the failing test.Akira Hatanaka2012-04-041-4/+4
| | | | llvm-svn: 154062
* Revert r154038. It was causing make check failures.Owen Anderson2012-04-041-4/+4
| | | | llvm-svn: 154054
* Fix LowerGlobalAddress to produce instructions with the correct relocationAkira Hatanaka2012-04-041-4/+4
| | | | | | types for N32 ABI. Add new test case and update existing ones. llvm-svn: 154038
* Change names for MIPS "generic" processors defined in Mips.td to match what GNUAkira Hatanaka2011-11-291-2/+2
| | | | | | | | | | tools use. Patch by Simon Atanasyan. "mips32r1" => "mips32" "4ke" => mips32r2" "mips64r1" => "mips64" llvm-svn: 145451
* Test cases for 64-bit load and store instructions.Akira Hatanaka2011-10-111-0/+58
llvm-svn: 141631
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